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bh=qSSGiIxpsfKrAO30RF0erGNPwh25M6eX6K+gQq2GDXk=; b=saJgYj6l3T9/NXqtCFUZps/xV8j5NDP5LAmnL1jpCwjt4UvskgRw4ncqbpIFLqK3df yPRK8jN0cD+IKKA6EWRhkPx3usvSQM6rS60cmKgqYoGwrSQtm+vN/+4gZWgeXhVydFC5 /bERcY6OeD0VE8e8CDi3NNz03L/jCVJgbbiYxj74GkOkNjolRVnd4qWrENCVFtDFToqS MARVMX+3W4y+rv/xCahxySHOVoc5QXlGvLH3llcxZPb0h4Rxweg1HjLnKNIi8Ok0ptWQ MUSlqPBodKBVER2Ph+OPHAMLtaB2FwU7RQiPiMg8n7BXVYXEwM4Z28sQaRADAg4nCwMB RgGA== X-Gm-Message-State: AJaThX46mRfdjNFpFumwt+rZVM3adtrLucM9UrhLSX2fBeDgOIWgYFt0 o5+SS//BokjYxA4UXRC7KEKvyR9AxEY= X-Google-Smtp-Source: ABhQp+RiiHvsmNsifVMLEqKH4/92xHK3owrNGgLwkWFKq7GlVycB1zNkoVrqW/rAGnCbe0yw1OAdtQ== X-Received: by 10.36.73.164 with SMTP id e36mr666840itd.129.1509729184960; Fri, 03 Nov 2017 10:13:04 -0700 (PDT) Received: from samitolvanen.mtv.corp.google.com ([100.98.112.14]) by smtp.gmail.com with ESMTPSA id d186sm1370787itd.38.2017.11.03.10.13.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:13:04 -0700 (PDT) From: Sami Tolvanen To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/15] arm64: fix mrs_s/msr_s macros for clang LTO Date: Fri, 3 Nov 2017 10:12:01 -0700 Message-Id: <20171103171203.107569-18-samitolvanen@google.com> X-Mailer: git-send-email 2.15.0.403.gc27cc4dac6-goog In-Reply-To: <20171103171203.107569-1-samitolvanen@google.com> References: <20171103171203.107569-1-samitolvanen@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171103_171322_900356_AD6796D9 X-CRM114-Status: GOOD ( 13.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sami Tolvanen , Matthias Kaehlcke , Nick Desaulniers , Kees Cook , Greg Hackmann MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Clang's integrated assembler does not allow assembly macros defined in one inline asm block using the .macro directive to be used across separate asm blocks. LLVM developers consider this a feature and not a bug, recommending code refactoring: https://bugs.llvm.org/show_bug.cgi?id=19749 As binutils doesn't allow macros to be redefined, this change adds C preprocessor macros that define the assembly macros globally for binutils and locally for clang's integrated assembler. Suggested-by: Greg Hackmann Suggested-by: Nick Desaulniers Signed-off-by: Sami Tolvanen --- arch/arm64/include/asm/kvm_hyp.h | 2 ++ arch/arm64/include/asm/sysreg.h | 71 ++++++++++++++++++++++++++++++---------- 2 files changed, 56 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 4572a9b560fa..6840704ea894 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -29,6 +29,7 @@ ({ \ u64 reg; \ asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\ + DEFINE_MRS_S \ "mrs_s %0, " __stringify(r##vh),\ ARM64_HAS_VIRT_HOST_EXTN) \ : "=r" (reg)); \ @@ -39,6 +40,7 @@ do { \ u64 __val = (u64)(v); \ asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\ + DEFINE_MSR_S \ "msr_s " __stringify(r##vh) ", %x0",\ ARM64_HAS_VIRT_HOST_EXTN) \ : : "rZ" (__val)); \ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f707fed5886f..1588ac3f3690 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -463,21 +463,58 @@ #include -asm( -" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" -" .equ .L__reg_num_x\\num, \\num\n" -" .endr\n" +#define ___MRS_MSR_S_REGNUM \ +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ +" .equ .L__reg_num_x\\num, \\num\n" \ +" .endr\n" \ " .equ .L__reg_num_xzr, 31\n" -"\n" -" .macro mrs_s, rt, sreg\n" - __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) + +#define ___MRS_S \ +" .macro mrs_s, rt, sreg\n" \ + __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ " .endm\n" -"\n" -" .macro msr_s, sreg, rt\n" - __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) + +#define ___MSR_S \ +" .macro msr_s, sreg, rt\n" \ + __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ " .endm\n" + +/* + * llvm-as doesn't allow macros defined in an asm block to be used in other + * asm blocks, which means we cannot define them globally. + */ +#if !defined(CONFIG_CLANG_LTO) +asm( + ___MRS_MSR_S_REGNUM + ___MRS_S + ___MSR_S ); +#undef ___MRS_MSR_S_REGNUM +#define ___MRS_MSR_S_REGNUM +#undef ___MRS_S +#define ___MRS_S +#undef ___MSR_S +#define ___MSR_S +#endif + +#define DEFINE_MRS_S \ + ___MRS_MSR_S_REGNUM \ + ___MRS_S + +#define DEFINE_MSR_S \ + ___MRS_MSR_S_REGNUM \ + ___MSR_S + + +#define __mrs_s(r, v) \ + DEFINE_MRS_S \ +" mrs_s %0, " __stringify(r) : "=r" (v) + +#define __msr_s(r, v) \ + DEFINE_MSR_S \ +" msr_s " __stringify(r) ", %0" : : "r" (v) + /* * Unlike read_cpuid, calls to read_sysreg are never expected to be * optimized away or replaced with synthetic values. @@ -502,15 +539,15 @@ asm( * For registers without architectural names, or simply unsupported by * GAS. */ -#define read_sysreg_s(r) ({ \ - u64 __val; \ - asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ - __val; \ +#define read_sysreg_s(r) ({ \ + u64 __val; \ + asm volatile(__mrs_s(r, __val)); \ + __val; \ }) -#define write_sysreg_s(v, r) do { \ - u64 __val = (u64)(v); \ - asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ +#define write_sysreg_s(v, r) do { \ + u64 __val = (u64)(v); \ + asm volatile(__msr_s(r, __val)); \ } while (0) static inline void config_sctlr_el1(u32 clear, u32 set)