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bh=t9Ksgh4OyQwQafylTBbV44o+XAMsyJqZVWC/Q992VB0=; b=Fy1eRv/7nwQBzyFtk5tv+jkJC0n5YNcOWM37UmngmZYjLK4OrJ5d6AyGlSdq3hgcbY qHLam6EhVTUOkE0zbuMW9NPAj5qPUisiBwgHuiQ7EliOvDVrNRPfclICrHhQGLxwvf+S toAvuWlZKUGTZTGglqWXYQLsrKUzKhP1/ayU0zS+kwJI56RTxioUbPQTu8JUYivi7PyV v9KTvFIznCkLRoGcDFxDcN4sMbKCTsQQE5JTUC7bv3eFL8oT4+G8CXgx7ovMpdEHnFp7 c+1u8Hn4osRdtkPRePMTIBSr9Vdhj2/BgWQe998/JL8AO5Tq4J3K/7PdaoDhv4XLPi8Z /ghg== X-Gm-Message-State: AJaThX4HwEeRQmq2NBUmBT1Nz9y1PvnKCwX7bPQ2AE3V/i18tTpFe/Kj 3+4v0IAwG0uNPNBDwKyW/LIIOw== X-Google-Smtp-Source: AGs4zMY15jDEiglodvTnMtxnGsxi63pt2JBR5mPqAU8D1MrEXIgXltKhfkBugGzOU6Xnuxm5GWEioA== X-Received: by 10.36.254.71 with SMTP id w68mr1004853ith.24.1512004050687; Wed, 29 Nov 2017 17:07:30 -0800 (PST) Received: from google.com ([2620:0:1000:1600:4c49:1dd8:1cd3:15b8]) by smtp.gmail.com with ESMTPSA id 14sm1382791ior.48.2017.11.29.17.07.29 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 29 Nov 2017 17:07:29 -0800 (PST) Date: Wed, 29 Nov 2017 17:07:27 -0800 From: Brian Norris To: Heiko Stuebner Subject: [PATCH] arm64: dts: rockchip: add rk3399 DSI0 reset Message-ID: <20171130010723.GA133459@google.com> References: <20171129233541.51337-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20171129233541.51337-1-briannorris@chromium.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171129_170752_720799_EC67932B X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Doug Anderson , linux-rockchip@lists.infradead.org, Nickey Yang , mka@chromium.org, Chris Zhong , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Nickey Yang This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang Signed-off-by: Brian Norris --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8940a3dc3670..e7e882d06c68 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1526,6 +1526,11 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopl>; + }; }; }; @@ -1573,6 +1578,11 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopb>; + }; }; }; @@ -1674,6 +1684,41 @@ }; }; + mipi_dsi1: mipi@ff968000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff968000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi1>; + }; + + mipi1_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi1>; + }; + }; + }; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>;