From patchwork Thu Dec 7 10:54:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 10098437 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 713FF60325 for ; Thu, 7 Dec 2017 10:55:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 596C92A417 for ; Thu, 7 Dec 2017 10:55:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D9B72A419; Thu, 7 Dec 2017 10:55:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E31BF2A417 for ; Thu, 7 Dec 2017 10:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=v+tcbZ6LZ+8QvcWoYAJAGCGQwNwLe6KQIbpPozsaOfo=; b=N1G6nLNcjc7Tjl3ZgGxY6SY7RT z5E484c1zHpqyjjckJ2XpGN1MOJETuYwIGbh/UHsmT8p9BDBQVMYCelU6x39hX+Y9jgB2GGRV4ljT b0A+7UASp2FBYsbDTKIn47SHcEZ3Ckx54pBaVrQ83DYTfBYVvPHKocOyqU9dRoA+TBrZTLb02DQ+Q lrHL8ol3cKhemNaRdLvBncQisCts/fNaYyRDmS3C7jugUkPq8dD14e424B1+T0OrDyNLec9Rf8ru9 W6dbI9P1q1o32QRlIRUbmanqsOcldgm/2hjw7fhuL3cRCIOxgwK4sQMROnLhaKy3sj8l2U5nJ7PwF 1ucmCTyQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eMtqH-0002KV-6n; Thu, 07 Dec 2017 10:55:49 +0000 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eMtpJ-00005e-S7 for linux-arm-kernel@lists.infradead.org; Thu, 07 Dec 2017 10:55:05 +0000 Received: by mail-wm0-x241.google.com with SMTP id n138so12248687wmg.2 for ; Thu, 07 Dec 2017 02:54:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f4/+CGNKF2zJ9jFBrM9M5rkwuvsY9KHB4qpHEQ2CX10=; b=PE9orS9Ca97xIJzvLYNCE8TMgmXnZ0ZVzALMP6vIdAaopG0NrAH1Zbcrj6wiMjLQbk zlPYSYvWVW6ytHjG5Prvy7T2IQmHyW7GodS1DU6fgG3/OQ312XY+EEhuUuwwxOGPf1Xk bYFXGH/xqh/aX9tWygDSwYSbriNd7PqPdSYuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f4/+CGNKF2zJ9jFBrM9M5rkwuvsY9KHB4qpHEQ2CX10=; b=KCqXPUYeHznCOWXJHsxnAlDf3qMJSbaoRby4X957gr9got2/e27AHv+wONQ71FeYVA 0hdnmqdBkJWufDFl0CIajQSR3LzyF6N8lKJVlO3VKEfPnhYE6OdemEYcrE3gKKGyZjWZ 5fZBhsB/BaF4h91FSnsUpaiPeqCFeWF/XroUkLb1N1wDBMSRCUo8MRG6TDfdFryUh/Mv X+sEd5PQ4AqxP/FbpNMDJZ61pq9EXENxD4gIlVG3xCWXheowlzApcyfbm/HBaMciqSpW EC/Fn4MTWZVbZM6LJnOzxkjUqlv6tM3AM2I2giVX9GWYJAH90y5fguTwxco9FsXmhtfL gAiQ== X-Gm-Message-State: AJaThX7UIjiu4GwQEqvn3zS3COONNa8384RSZXolShUiU1xbCBPuPjZk 58YyK0C+fEkRMIgodqdO5EpWAuYQ81c= X-Google-Smtp-Source: AGs4zMYmK9+cTrzIRpHSQFSKEQn2g0fY38O2tn2fYu7DVCHkOmneeUdVlEQrrNmlm0TY3PvzDOl45Q== X-Received: by 10.80.142.17 with SMTP id 17mr46249211edw.147.1512644073091; Thu, 07 Dec 2017 02:54:33 -0800 (PST) Received: from localhost.localdomain (x50d2404e.cust.hiper.dk. [80.210.64.78]) by smtp.gmail.com with ESMTPSA id t23sm2233671edb.70.2017.12.07.02.54.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:54:32 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v7 3/8] KVM: arm/arm64: Don't cache the timer IRQ level Date: Thu, 7 Dec 2017 11:54:13 +0100 Message-Id: <20171207105418.22428-4-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171207105418.22428-1-christoffer.dall@linaro.org> References: <20171207105418.22428-1-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171207_025450_596786_9BE6149A X-CRM114-Status: GOOD ( 18.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Marc Zyngier , Andre Przywara , Eric Auger , linux-arm-kernel@lists.infradead.org, Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The timer was modeled after a strict idea of modelling an interrupt line level in software, meaning that only transitions in the level needed to be reported to the VGIC. This works well for the timer, because the arch timer code is in complete control of the device and can track the transitions of the line. However, as we are about to support using the HW bit in the VGIC not just for the timer, but also for VFIO which cannot track transitions of the interrupt line, we have to decide on an interface for level triggered mapped interrupts to the GIC, which both the timer and VFIO can use. VFIO only sees an asserting transition of the physical interrupt line, and tells the VGIC when that happens. That means that part of the interrupt flow is offloaded to the hardware. To use the same interface for VFIO devices and the timer, we therefore have to change the timer (we cannot change VFIO because it doesn't know the details of the device it is assigning to a VM). Luckily, changing the timer is simple, we just need to stop 'caching' the line level, but instead let the VGIC know the state of the timer every time there is a potential change in the line level, and when the line level should be asserted from the timer ISR. The VGIC can ignore extra notifications using its validate mechanism. Reviewed-by: Andre Przywara Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 4151250ce8da..dd5aca05c500 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -99,11 +99,9 @@ static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id) } vtimer = vcpu_vtimer(vcpu); - if (!vtimer->irq.level) { - vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl); - if (kvm_timer_irq_can_fire(vtimer)) - kvm_timer_update_irq(vcpu, true, vtimer); - } + vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl); + if (kvm_timer_irq_can_fire(vtimer)) + kvm_timer_update_irq(vcpu, true, vtimer); if (unlikely(!irqchip_in_kernel(vcpu->kvm))) kvm_vtimer_update_mask_user(vcpu); @@ -324,12 +322,20 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu) struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); + bool level; if (unlikely(!timer->enabled)) return; - if (kvm_timer_should_fire(vtimer) != vtimer->irq.level) - kvm_timer_update_irq(vcpu, !vtimer->irq.level, vtimer); + /* + * The vtimer virtual interrupt is a 'mapped' interrupt, meaning part + * of its lifecycle is offloaded to the hardware, and we therefore may + * not have lowered the irq.level value before having to signal a new + * interrupt, but have to signal an interrupt every time the level is + * asserted. + */ + level = kvm_timer_should_fire(vtimer); + kvm_timer_update_irq(vcpu, level, vtimer); if (kvm_timer_should_fire(ptimer) != ptimer->irq.level) kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer);