Message ID | 20171219080747.4507-4-embed3d@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[91.61.219.101]) by smtp.gmail.com with ESMTPSA id c34sm15820113wra.53.2017.12.19.00.07.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Dec 2017 00:07:53 -0800 (PST) From: Philipp Rossak <embed3d@gmail.com> To: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, sean@mess.org, p.zabel@pengutronix.de, andi.shyti@samsung.com Subject: [PATCH v3 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T Date: Tue, 19 Dec 2017 09:07:44 +0100 Message-Id: <20171219080747.4507-4-embed3d@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219080747.4507-1-embed3d@gmail.com> References: <20171219080747.4507-1-embed3d@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171219_000806_044254_36C37CBC X-CRM114-Status: UNSURE ( 9.17 ) X-CRM114-Notice: Please train this message. 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diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index de5119a2a91c..06e96db7c41a 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -617,6 +617,11 @@ interrupt-controller; #interrupt-cells = <3>; + cir_pins: cir-pins@0 { + pins = "PL12"; + function = "s_cir_rx"; + }; + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb";
The CIR Pin of the A83T is located at PL12. Signed-off-by: Philipp Rossak <embed3d@gmail.com> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++ 1 file changed, 5 insertions(+)