From patchwork Fri Dec 29 10:55:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mylene JOSSERAND X-Patchwork-Id: 10136993 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 643456037D for ; Fri, 29 Dec 2017 10:57:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 642B32CD43 for ; Fri, 29 Dec 2017 10:57:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 55E462CDCF; Fri, 29 Dec 2017 10:57:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D2272CD43 for ; Fri, 29 Dec 2017 10:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mnApvaIay6mKRTuAcuM/ELnCrm5nDLcXKfGfmhFAWGo=; b=ZFiDddgboZ9qo6 unqYCsqDI8zSuc31ucauW+DERDSNrI+5AaePYJIXUUEM7lAwmqGmQUvmjjMa92T2M04olfFvVF1p4 2bfNaJIBPj8K6D6ZzSQZN4XNv5mzGgyF5cM+C0d3rOkcAjYMfWuB9ANoJ1p04v+J85TLcyIExn5Iu iTD/QGmiMcyOypZF2f0Sg/SRJ5TOcu+1UUiAaEAlU3+t4mhYtCvvzJ8ZpdPCzklo/D1uTyqXcUkBE ILagl0D9pvcFRtZKca7KXISRHp9/BrfxyE8KmhNNySsaYxqqM+Du6y4zde1fQ3iqZW+kqOEY4kyXD KCulx+wKT7JrHz138E/w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eUsM5-000893-IF; Fri, 29 Dec 2017 10:57:37 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eUsKH-0006w9-66 for linux-arm-kernel@lists.infradead.org; Fri, 29 Dec 2017 10:55:50 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 6841720731; Fri, 29 Dec 2017 11:55:32 +0100 (CET) Received: from dell-desktop.lan (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0F07A20737; Fri, 29 Dec 2017 11:55:22 +0100 (CET) From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= To: maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v2 2/5] ARM: sunxi: mcpm: Add support for A83T Date: Fri, 29 Dec 2017 11:55:03 +0100 Message-Id: <20171229105506.24851-3-mylene.josserand@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171229105506.24851-1-mylene.josserand@free-electrons.com> References: <20171229105506.24851-1-mylene.josserand@free-electrons.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171229_025545_610677_8D3EC94B X-CRM114-Status: GOOD ( 18.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.petazzoni@free-electrons.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quentin.schulz@free-electrons.com, clabbe.montjoie@gmail.com, mylene.josserand@free-electrons.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the support for A83T. A83T SoC has an additional register than A80 to handle CPU configurations: R_CPUS_CFG. Information about the register comes from Allwinner's BSP driver. An important difference is the Power Off Gating register for clusters which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T. Signed-off-by: Mylène Josserand --- arch/arm/mach-sunxi/Kconfig | 1 + arch/arm/mach-sunxi/mcpm.c | 142 ++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 133 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 177380548d99..ae7b57fbd7ac 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -42,6 +42,7 @@ config MACH_SUN8I default ARCH_SUNXI select ARM_GIC select MFD_SUN6I_PRCM + imply MCPM config MACH_SUN9I bool "Allwinner (sun9i) SoCs support" diff --git a/arch/arm/mach-sunxi/mcpm.c b/arch/arm/mach-sunxi/mcpm.c index 4b6e1d6ae379..716a888df70e 100644 --- a/arch/arm/mach-sunxi/mcpm.c +++ b/arch/arm/mach-sunxi/mcpm.c @@ -43,17 +43,25 @@ #define CPUCFG_CX_RST_CTRL_L2_RST BIT(8) #define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n)) #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n) +#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0) #define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c)) #define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n) #define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf #define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c)) -#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4) +/* The power off register for clusters are different from SUN9I and SUN8I */ +#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0) +#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4) #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n) #define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu)) #define PRCM_CPU_SOFT_ENTRY_REG 0x164 +#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4) +#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n) +#define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4 + static void __iomem *cpucfg_base; +static void __iomem *r_cpucfg_base; static void __iomem *prcm_base; static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster, @@ -101,6 +109,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster) reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu); writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); + if (r_cpucfg_base) { + /* assert cpu power-on reset */ + reg = readl(r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu)); + writel(reg, r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + udelay(10); + } + /* Cortex-A7: hold L1 reset disable signal low */ if (!(of_machine_is_compatible("allwinner,sun9i-a80") && cluster == SUN9I_A80_A15_CLUSTER)) { @@ -126,17 +144,37 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster) /* open power switch */ sunxi_cpu_power_switch_set(cpu, cluster, true); + /* Handle A83T bit swap */ + if (of_machine_is_compatible("allwinner,sun8i-a83t")) { + if (cpu == 0) + cpu = 4; + } + /* clear processor power gate */ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu); writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); udelay(20); + if (of_machine_is_compatible("allwinner,sun8i-a83t")) { + if (cpu == 4) + cpu = 0; + } + /* de-assert processor power-on reset */ reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu); writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); + if (r_cpucfg_base) { + reg = readl(r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu); + writel(reg, r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + udelay(10); + } + /* de-assert all processor resets */ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu); @@ -160,6 +198,14 @@ static int sunxi_cluster_powerup(unsigned int cluster) if (cluster >= SUNXI_NR_CLUSTERS) return -EINVAL; + /* For A83T, assert cluster cores resets */ + if (of_machine_is_compatible("allwinner,sun8i-a83t")) { + reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); + reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */ + writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); + udelay(10); + } + /* assert ACINACTM */ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg |= CPUCFG_CX_CTRL_REG1_ACINACTM; @@ -170,6 +216,16 @@ static int sunxi_cluster_powerup(unsigned int cluster) reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL; writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); + /* assert cluster cores resets */ + if (r_cpucfg_base) { + reg = readl(r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; + writel(reg, r_cpucfg_base + + R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); + udelay(10); + } + /* assert cluster resets */ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST; @@ -202,7 +258,10 @@ static int sunxi_cluster_powerup(unsigned int cluster) /* clear cluster power gate */ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); - reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER; + if (of_machine_is_compatible("allwinner,sun8i-a83t")) + reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I; + else + reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I; writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); udelay(20); @@ -327,23 +386,54 @@ static void __naked sunxi_power_up_setup(unsigned int affinity_level) static void sunxi_mcpm_setup_entry_point(void) { - __raw_writel(virt_to_phys(mcpm_entry_point), - prcm_base + PRCM_CPU_SOFT_ENTRY_REG); + if (of_machine_is_compatible("allwinner,sun9i-a80")) + __raw_writel(virt_to_phys(mcpm_entry_point), + prcm_base + PRCM_CPU_SOFT_ENTRY_REG); + else + __raw_writel(virt_to_phys(mcpm_entry_point), r_cpucfg_base + + R_CPUCFG_CPU_SOFT_ENTRY_REG); } -static int __init sunxi_mcpm_init(void) +static int sun9i_dt_parsing(void) { struct device_node *node; - int ret; - if (!of_machine_is_compatible("allwinner,sun9i-a80")) + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun9i-a80-cpucfg"); + if (!node) return -ENODEV; - if (!cci_probed()) + cpucfg_base = of_iomap(node, 0); + of_node_put(node); + if (!cpucfg_base) { + pr_err("%s: failed to map CPUCFG registers\n", __func__); + return -ENOMEM; + } + + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun9i-a80-prcm"); + if (!node) return -ENODEV; + prcm_base = of_iomap(node, 0); + of_node_put(node); + if (!prcm_base) { + pr_err("%s: failed to map PRCM registers\n", __func__); + iounmap(prcm_base); + return -ENOMEM; + } + + r_cpucfg_base = NULL; + + return 0; +} + +static int sun8i_dt_parsing(void) +{ + struct device_node *node; + node = of_find_compatible_node(NULL, NULL, - "allwinner,sun9i-a80-cpucfg"); + "allwinner,sun8i-a83t-cpucfg"); if (!node) return -ENODEV; @@ -355,7 +445,7 @@ static int __init sunxi_mcpm_init(void) } node = of_find_compatible_node(NULL, NULL, - "allwinner,sun9i-a80-prcm"); + "allwinner,sun8i-a83t-prcm"); if (!node) return -ENODEV; @@ -367,6 +457,38 @@ static int __init sunxi_mcpm_init(void) return -ENOMEM; } + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun8i-a83t-r-cpucfg"); + if (!node) + return -ENODEV; + + r_cpucfg_base = of_iomap(node, 0); + of_node_put(node); + if (!r_cpucfg_base) { + pr_err("%s: failed to map R-CPUCFG registers\n", + __func__); + return -ENOMEM; + } + + return 0; +} + +static int __init sunxi_mcpm_init(void) +{ + int ret; + + if (!of_machine_is_compatible("allwinner,sun9i-a80") && + !of_machine_is_compatible("allwinner,sun8i-a83t")) + return -ENODEV; + + if (!cci_probed()) + return -ENODEV; + + if (of_machine_is_compatible("allwinner,sun9i-a80")) + ret = sun9i_dt_parsing(); + else + ret = sun8i_dt_parsing(); + ret = mcpm_platform_register(&sunxi_power_ops); if (!ret) ret = mcpm_sync_init(sunxi_power_up_setup);