From patchwork Sat Dec 30 11:30:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10137707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 297896056F for ; Sat, 30 Dec 2017 11:35:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 208A829463 for ; Sat, 30 Dec 2017 11:35:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11D9229633; Sat, 30 Dec 2017 11:35:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6AE7629628 for ; Sat, 30 Dec 2017 11:35:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=V8jj7JzeiEtr9A2xwIkkxwJE5IteytPFNzZewDXBkrk=; b=jsnOmdOqLG24Be5OwEi34GM3hO Gv//9mXdgFN+uQTleT43PSh+yReYkSIpGWOJTdC23GseBR2y8qDEsN5SqdSqgm2NbVx+PSZISinEN BARwkqc79v2krURR/9r0tfkB5RKc12326HGSZFqdZyYHQ0nlW266w6NsIxtUON2Hm5ndMwTl07TA5 Ht6lz1evoGYXSHireMTgqgdv9wbCmiN1pUG+7SyS94DSChbu8Z1vJ4tWqjcBW11Qc+Lz6Jj5i7Udu Tl/aXHNJQGpXWTBa5/vF8SXzbVMnuHCcXZ5BetAYA/4SXcDlf2eXZylCpWFBhp8+1oBj9U/htVQsn Ui/5DIsA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eVFQ3-0004tW-Ot; Sat, 30 Dec 2017 11:35:15 +0000 Received: from coral.maple.relay.mailchannels.net ([23.83.214.39]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1eVFO9-0003zY-WD for linux-arm-kernel@lists.infradead.org; Sat, 30 Dec 2017 11:33:26 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id DA6F63E112B; Sat, 30 Dec 2017 11:33:06 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.16.28]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id 07C2F3E10C1; Sat, 30 Dec 2017 11:33:05 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.18.55.125]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.11.3); Sat, 30 Dec 2017 11:33:06 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Irritate-Cooing: 508fef1e562821e7_1514633586569_3464371048 X-MC-Loop-Signature: 1514633586569:2609364197 X-MC-Ingress-Time: 1514633586568 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 086784754A; Sat, 30 Dec 2017 11:33:01 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v4 3/6] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU Date: Sat, 30 Dec 2017 19:30:40 +0800 Message-Id: <20171230113043.30237-4-icenowy@aosc.io> In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io> References: <20171230113043.30237-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171230_033319_142707_A6ED941B X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v4: - Use a struct to maintain both ccu desc and quirks as Chen-Yu Tsai suggested. drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 117 +++++++++++++++++++++++------------ 1 file changed, 77 insertions(+), 40 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 468d1abaf0ee..b65953b32bd0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_div.h" @@ -156,44 +157,70 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = { [RST_WB] = { 0x08, BIT(2) }, }; -static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { - .ccu_clks = sun8i_a83t_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), +struct de2_ccu { + struct sunxi_ccu_desc desc; + bool sram_needed; +}; + +static const struct de2_ccu sun8i_a83t_de2_clk = { + .desc = { + .ccu_clks = sun8i_a83t_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), + + .hw_clks = &sun8i_a83t_de2_hw_clks, + + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + }, +}; + +static const struct de2_ccu sun8i_h3_de2_clk = { + .desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), - .hw_clks = &sun8i_a83t_de2_hw_clks, + .hw_clks = &sun8i_h3_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + }, }; -static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { - .ccu_clks = sun8i_h3_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), +static const struct de2_ccu sun50i_a64_de2_clk = { + .desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), - .hw_clks = &sun8i_h3_de2_hw_clks, + .hw_clks = &sun8i_h3_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun50i_a64_de2_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), + }, + .sram_needed = true, }; -static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { - .ccu_clks = sun8i_h3_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), +static const struct de2_ccu sun50i_h5_de2_clk = { + .desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), - .hw_clks = &sun8i_h3_de2_hw_clks, + .hw_clks = &sun8i_h3_de2_hw_clks, - .resets = sun50i_a64_de2_resets, - .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), + .resets = sun50i_a64_de2_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), + }, }; -static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { - .ccu_clks = sun8i_v3s_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), +static const struct de2_ccu sun8i_v3s_de2_clk = { + .desc = { + .ccu_clks = sun8i_v3s_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), - .hw_clks = &sun8i_v3s_de2_hw_clks, + .hw_clks = &sun8i_v3s_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + }, }; static int sunxi_de2_clk_probe(struct platform_device *pdev) @@ -202,11 +229,11 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) struct clk *bus_clk, *mod_clk; struct reset_control *rstc; void __iomem *reg; - const struct sunxi_ccu_desc *ccu_desc; + const struct de2_ccu *ccu; int ret; - ccu_desc = of_device_get_match_data(&pdev->dev); - if (!ccu_desc) + ccu = of_device_get_match_data(&pdev->dev); + if (!ccu) return -EINVAL; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -239,11 +266,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) return ret; } + if (ccu->sram_needed) { + ret = sunxi_sram_claim(&pdev->dev); + if (ret) { + dev_err(&pdev->dev, + "Error couldn't map SRAM to device\n"); + return ret; + } + } + /* The clocks need to be enabled for us to access the registers */ ret = clk_prepare_enable(bus_clk); if (ret) { dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); - return ret; + goto err_release_sram; } ret = clk_prepare_enable(mod_clk); @@ -260,7 +296,7 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) goto err_disable_mod_clk; } - ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc); + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &ccu->desc); if (ret) goto err_assert_reset; @@ -272,33 +308,34 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) clk_disable_unprepare(mod_clk); err_disable_bus_clk: clk_disable_unprepare(bus_clk); +err_release_sram: + if (ccu->sram_needed) + sunxi_sram_release(&pdev->dev); + return ret; } static const struct of_device_id sunxi_de2_clk_ids[] = { { .compatible = "allwinner,sun8i-a83t-de2-clk", - .data = &sun8i_a83t_de2_clk_desc, + .data = &sun8i_a83t_de2_clk, }, { .compatible = "allwinner,sun8i-h3-de2-clk", - .data = &sun8i_h3_de2_clk_desc, + .data = &sun8i_h3_de2_clk, }, { .compatible = "allwinner,sun8i-v3s-de2-clk", - .data = &sun8i_v3s_de2_clk_desc, + .data = &sun8i_v3s_de2_clk, + }, + { + .compatible = "allwinner,sun50i-a64-de2-clk", + .data = &sun50i_a64_de2_clk, }, { .compatible = "allwinner,sun50i-h5-de2-clk", - .data = &sun50i_a64_de2_clk_desc, + .data = &sun50i_h5_de2_clk, }, - /* - * The Allwinner A64 SoC needs some bit to be poke in syscon to make - * DE2 really working. - * So there's currently no A64 compatible here. - * H5 shares the same reset line with A64, so here H5 is using the - * clock description of A64. - */ { } };