| Message ID | 20180115193906.30053-4-james.morse@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 15/01/18 19:38, James Morse wrote: > From: Xie XiuQi <xiexiuqi@huawei.com> > > ARM's v8.2 Extentions add support for Reliability, Availability and > Serviceability (RAS). On CPUs with these extensions system software > can use additional barriers to isolate errors and determine if faults > are pending. Add cpufeature detection. > > Platform level RAS support may require additional firmware support. > > Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> > [Rebased added config option, reworded commit message] > Signed-off-by: James Morse <james.morse@arm.com> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Hi James, On 2018/1/16 3:38, James Morse wrote: > From: Xie XiuQi <xiexiuqi@huawei.com> > > ARM's v8.2 Extentions add support for Reliability, Availability and > Serviceability (RAS). On CPUs with these extensions system software > can use additional barriers to isolate errors and determine if faults > are pending. Add cpufeature detection. > > Platform level RAS support may require additional firmware support. > > Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> > [Rebased added config option, reworded commit message] > Signed-off-by: James Morse <james.morse@arm.com> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> > --- > Changes since v4: > * Removed barrier in context switch > > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/include/asm/cpucaps.h | 3 ++- > arch/arm64/include/asm/sysreg.h | 2 ++ > arch/arm64/kernel/cpufeature.c | 13 +++++++++++++ > 4 files changed, 33 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 664fadc2aa2e..1d51c8edf34b 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1062,6 +1062,22 @@ config ARM64_PMEM > operations if DC CVAP is not supported (following the behaviour of > DC CVAP itself if the system does not define a point of persistence). > > +config ARM64_RAS_EXTN > + bool "Enable support for RAS CPU Extensions" > + default y > + help > + CPUs that support the Reliability, Availability and Serviceability > + (RAS) Extensions, part of ARMv8.2 are able to track faults and > + errors, classify them and report them to software. > + > + On CPUs with these extensions system software can use additional > + barriers to determine if faults are pending and read the > + classification from a new set of registers. > + > + Selecting this feature will allow the kernel to use these barriers > + and access the new registers if the system supports the extension. > + Platform RAS features may additionally depend on firmware support. > + > endmenu > it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the "arch/arm64/configs/defconfig", if not, I want to enable this config to enable RAS feature in the defconfig. do you agree? thanks > config ARM64_SVE > diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h > index 7049b4802587..bb263820de13 100644 > --- a/arch/arm64/include/asm/cpucaps.h > +++ b/arch/arm64/include/asm/cpucaps.h > @@ -44,7 +44,8 @@ > #define ARM64_UNMAP_KERNEL_AT_EL0 23 > #define ARM64_HARDEN_BRANCH_PREDICTOR 24 > #define ARM64_HARDEN_BP_POST_GUEST_EXIT 25 > +#define ARM64_HAS_RAS_EXTN 26 > > -#define ARM64_NCAPS 26 > +#define ARM64_NCAPS 27 > > #endif /* __ASM_CPUCAPS_H */ > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 1a8108f84932..321622e9f9c3 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -498,6 +498,7 @@ > #define ID_AA64PFR0_CSV3_SHIFT 60 > #define ID_AA64PFR0_CSV2_SHIFT 56 > #define ID_AA64PFR0_SVE_SHIFT 32 > +#define ID_AA64PFR0_RAS_SHIFT 28 > #define ID_AA64PFR0_GIC_SHIFT 24 > #define ID_AA64PFR0_ASIMD_SHIFT 20 > #define ID_AA64PFR0_FP_SHIFT 16 > @@ -507,6 +508,7 @@ > #define ID_AA64PFR0_EL0_SHIFT 0 > > #define ID_AA64PFR0_SVE 0x1 > +#define ID_AA64PFR0_RAS_V1 0x1 > #define ID_AA64PFR0_FP_NI 0xf > #define ID_AA64PFR0_FP_SUPPORTED 0x0 > #define ID_AA64PFR0_ASIMD_NI 0xf > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index d88cd0e88606..0c0af18121e1 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -149,6 +149,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), > S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), > S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), > @@ -1028,6 +1029,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .enable = sve_kernel_enable, > }, > #endif /* CONFIG_ARM64_SVE */ > +#ifdef CONFIG_ARM64_RAS_EXTN > + { > + .desc = "RAS Extension Support", > + .capability = ARM64_HAS_RAS_EXTN, > + .def_scope = SCOPE_SYSTEM, > + .matches = has_cpuid_feature, > + .sys_reg = SYS_ID_AA64PFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64PFR0_RAS_SHIFT, > + .min_field_value = ID_AA64PFR0_RAS_V1, > + }, > +#endif /* CONFIG_ARM64_RAS_EXTN */ > {}, > }; > >
Hi gengdongjiu, On 16/01/18 11:17, gengdongjiu wrote: > Hi James, > > On 2018/1/16 3:38, James Morse wrote: >> From: Xie XiuQi <xiexiuqi@huawei.com> >> >> ARM's v8.2 Extentions add support for Reliability, Availability and >> Serviceability (RAS). On CPUs with these extensions system software >> can use additional barriers to isolate errors and determine if faults >> are pending. Add cpufeature detection. >> >> Platform level RAS support may require additional firmware support. >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 664fadc2aa2e..1d51c8edf34b 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -1062,6 +1062,22 @@ config ARM64_PMEM >> operations if DC CVAP is not supported (following the behaviour of >> DC CVAP itself if the system does not define a point of persistence). >> >> +config ARM64_RAS_EXTN >> + bool "Enable support for RAS CPU Extensions" >> + default y >> + help >> + CPUs that support the Reliability, Availability and Serviceability >> + (RAS) Extensions, part of ARMv8.2 are able to track faults and >> + errors, classify them and report them to software. >> + >> + On CPUs with these extensions system software can use additional >> + barriers to determine if faults are pending and read the >> + classification from a new set of registers. >> + >> + Selecting this feature will allow the kernel to use these barriers >> + and access the new registers if the system supports the extension. >> + Platform RAS features may additionally depend on firmware support. >> + >> endmenu >> > it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the "arch/arm64/configs/defconfig", > if not, I want to enable this config to enable RAS feature in the defconfig. do you agree? Sure. This series doesn't do a lot on its own, it expects firmware-first or kernel-first support, which may in turn depend-on this feature. It means we don't panic() when notified of corrected errors, until we get the {firmware,kernel}-first support. Don't defconfig changes get collected by arm-soc? (I'm not sure how these get picked up...) James
Hi James, On 2018/1/23 3:32, James Morse wrote: >> it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the "arch/arm64/configs/defconfig", >> if not, I want to enable this config to enable RAS feature in the defconfig. do you agree? > Sure. This series doesn't do a lot on its own, it expects firmware-first or > kernel-first support, which may in turn depend-on this feature. It means we > don't panic() when notified of corrected errors, until we get the > {firmware,kernel}-first support. > > Don't defconfig changes get collected by arm-soc? (I'm not sure how these get > picked up...) Now we should have supported firmware-first, do you mean we do not enable "CONFIG_ARM64_RAS_EXTN" in the defconfig for ARM's SOC until kernel-first RAS is supported? > > > James
Hi gengdongjiu, On 23/01/18 09:06, gengdongjiu wrote: > On 2018/1/23 3:32, James Morse wrote: >>> it seems this "CONFIG_ARM64_RAS_EXTN" is not enabled in the "arch/arm64/configs/defconfig", >>> if not, I want to enable this config to enable RAS feature in the defconfig. do you agree? >> Sure. This series doesn't do a lot on its own, it expects firmware-first or >> kernel-first support, which may in turn depend-on this feature. It means we >> don't panic() when notified of corrected errors, until we get the >> {firmware,kernel}-first support. >> >> Don't defconfig changes get collected by arm-soc? (I'm not sure how these get >> picked up...) > > Now we should have supported firmware-first, For NOTIFY_SEI? We don't have that yet. This series was about the minimal handling for systems with neither firmware or kernel first handling. This stops us panic()ing on corrected errors. It also enables IESB which benefits firmware first handling using the notification types we already support. (SEA, POLL, IRQ etc) From here we can add KVM APIs, firmware-first notification support and kernel-first support as independent series. > do you mean we do not enable "CONFIG_ARM64_RAS_EXTN" in the > defconfig for ARM's SOC until kernel-first RAS is supported? I've no idea if or when we will do kernel-first, when I bring it up, its so we don't build a hybrid model, and we consider how we going to add kernel-first support if/when it comes along. If you want it turned on in defconfig please submit a patch to do that. I haven't because I don't know where they go! Thanks, James
On 2018/1/24 3:05, James Morse wrote: >> do you mean we do not enable "CONFIG_ARM64_RAS_EXTN" in the >> defconfig for ARM's SOC until kernel-first RAS is supported? > I've no idea if or when we will do kernel-first, when I bring it up, its so we > don't build a hybrid model, and we consider how we going to add kernel-first > support if/when it comes along. > > If you want it turned on in defconfig please submit a patch to do that. I sorry, it is my mistake, In your patch, ARM64_RAS_EXTN is already turned on by default, so no need to turn on again. +config ARM64_RAS_EXTN + bool "Enable support for RAS CPU Extensions" + default y + help + CPUs that support the Reliability, Availability and Serviceability > haven't because I don't know where they go!
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 664fadc2aa2e..1d51c8edf34b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1062,6 +1062,22 @@ config ARM64_PMEM operations if DC CVAP is not supported (following the behaviour of DC CVAP itself if the system does not define a point of persistence). +config ARM64_RAS_EXTN + bool "Enable support for RAS CPU Extensions" + default y + help + CPUs that support the Reliability, Availability and Serviceability + (RAS) Extensions, part of ARMv8.2 are able to track faults and + errors, classify them and report them to software. + + On CPUs with these extensions system software can use additional + barriers to determine if faults are pending and read the + classification from a new set of registers. + + Selecting this feature will allow the kernel to use these barriers + and access the new registers if the system supports the extension. + Platform RAS features may additionally depend on firmware support. + endmenu config ARM64_SVE diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 7049b4802587..bb263820de13 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -44,7 +44,8 @@ #define ARM64_UNMAP_KERNEL_AT_EL0 23 #define ARM64_HARDEN_BRANCH_PREDICTOR 24 #define ARM64_HARDEN_BP_POST_GUEST_EXIT 25 +#define ARM64_HAS_RAS_EXTN 26 -#define ARM64_NCAPS 26 +#define ARM64_NCAPS 27 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1a8108f84932..321622e9f9c3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -498,6 +498,7 @@ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_SVE_SHIFT 32 +#define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 @@ -507,6 +508,7 @@ #define ID_AA64PFR0_EL0_SHIFT 0 #define ID_AA64PFR0_SVE 0x1 +#define ID_AA64PFR0_RAS_V1 0x1 #define ID_AA64PFR0_FP_NI 0xf #define ID_AA64PFR0_FP_SUPPORTED 0x0 #define ID_AA64PFR0_ASIMD_NI 0xf diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d88cd0e88606..0c0af18121e1 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -149,6 +149,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), @@ -1028,6 +1029,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .enable = sve_kernel_enable, }, #endif /* CONFIG_ARM64_SVE */ +#ifdef CONFIG_ARM64_RAS_EXTN + { + .desc = "RAS Extension Support", + .capability = ARM64_HAS_RAS_EXTN, + .def_scope = SCOPE_SYSTEM, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64PFR0_RAS_SHIFT, + .min_field_value = ID_AA64PFR0_RAS_V1, + }, +#endif /* CONFIG_ARM64_RAS_EXTN */ {}, };