From patchwork Tue Jan 23 12:27:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 10180123 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EABC26019D for ; Tue, 23 Jan 2018 12:31:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAD0C205AD for ; Tue, 23 Jan 2018 12:31:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF7F22833E; Tue, 23 Jan 2018 12:31:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 58DB8205AD for ; Tue, 23 Jan 2018 12:31:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=e1wGW3ijkfEFlNIgusOJ10sv15Px1/8EkCel+1gddto=; b=VACIQh6MdBW+BpBRdhH5VE4ftW ntHU8V+ie9LbLj9NCr7On2bQrTskkqjSdmPf0MiczO2A7u7yP/zFlLnIFdzMc6BXPLSUVi8HEpA5u HBTygqYjFDZgUK2Is70BWE53NgQCL1+PlLhc1ZEJH7KSvHzVPZxFMJ1QKvh2jtzWQIIPyHCOb3D66 cbY2cl4UH/Yx45rrR+DxvhXOT8XRTqIv9y1sSB0m9G6dkjmDVzOMEWI6cc+3pcpRTXfmHq4BdVsdI KTakjOWspfB1XNLyrFXTfSqGdENEc7+P76IALOXF2Le7xEbMHBvTeplMZImBAoCpRYaUgmx5HFicX qjLtIOdA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1edxjk-0001Mu-Nz; Tue, 23 Jan 2018 12:31:36 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1edxh7-0005WP-Dh for linux-arm-kernel@lists.infradead.org; Tue, 23 Jan 2018 12:28:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D450164F; Tue, 23 Jan 2018 04:28:33 -0800 (PST) Received: from e107814-lin.cambridge.arm.com (e107814-lin.cambridge.arm.com [10.1.206.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C1BA83F318; Tue, 23 Jan 2018 04:28:31 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/16] arm64: Add flags to check the safety of a capability for late CPU Date: Tue, 23 Jan 2018 12:27:58 +0000 Message-Id: <20180123122809.16269-6-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180123122809.16269-1-suzuki.poulose@arm.com> References: <20180123122809.16269-1-suzuki.poulose@arm.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, ckadabi@codeaurora.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, Suzuki K Poulose , will.deacon@arm.com, linux-kernel@vger.kernel.org, jnair@caviumnetworks.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add two different flags to indicate if the conflict of a capability on a late CPU with the current system state 1) Can a CPU have a capability when the system doesn't have it ? Most arm64 features could have this set. While erratum work arounds cannot have this, as we may miss work arounds. 2) Can a CPU miss a capability when the system has it ? This could be set for arm64 erratum work arounds as we don't care if a CPU doesn't need the work around. However it should be clear for features. These flags could be added to certain entries based on their nature. Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/cpufeature.h | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 4fd5de8ef33e..27d037bb0451 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -94,10 +94,25 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU -/* CPU errata detected at boot time based on feature of one or more CPUs */ -#define ARM64_CPUCAP_STRICT_CPU_LOCAL_ERRATUM (ARM64_CPUCAP_SCOPE_LOCAL_CPU) -/* CPU feature detected at boot time based on system-wide value of a feature */ -#define ARM64_CPUCAP_BOOT_SYSTEM_FEATURE (ARM64_CPUCAP_SCOPE_SYSTEM) +/* Is it safe for a late CPU to have this capability when system doesn't already have */ +#define ARM64_CPUCAP_LATE_CPU_SAFE_TO_HAVE BIT(2) +/* Is it safe for a late CPU to miss this capability when system has it */ +#define ARM64_CPUCAP_LATE_CPU_SAFE_TO_MISS BIT(3) + +/* + * CPU errata detected at boot time based on feature of one or more CPUs. + * It is not safe for a late CPU to have this feature when the system doesn't + * have it. But it is safe to miss the feature if the system has it. + */ +#define ARM64_CPUCAP_STRICT_CPU_LOCAL_ERRATUM \ + (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_LATE_CPU_SAFE_TO_MISS) +/* + * CPU feature detected at boot time based on system-wide value of a feature. + * It is safe for a late CPU to have this feature even though the system doesn't + * have it already. But the CPU must have this feature if the system does. + */ +#define ARM64_CPUCAP_BOOT_SYSTEM_FEATURE \ + (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_LATE_CPU_SAFE_TO_HAVE) struct arm64_cpu_capabilities { const char *desc; @@ -128,6 +143,18 @@ static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) return cap->type & ARM64_CPUCAP_SCOPE_MASK; } +static inline bool +cpucap_late_cpu_missing_cap_safe(const struct arm64_cpu_capabilities *cap) +{ + return !!(cap->type & ARM64_CPUCAP_LATE_CPU_SAFE_TO_MISS); +} + +static inline bool +cpucap_late_cpu_have_cap_safe(const struct arm64_cpu_capabilities *cap) +{ + return !!(cap->type & ARM64_CPUCAP_LATE_CPU_SAFE_TO_HAVE); +} + extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS]; extern struct static_key_false arm64_const_caps_ready;