From patchwork Fri Feb 9 17:03:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 10209553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7AB7A60245 for ; Fri, 9 Feb 2018 17:04:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66A322975B for ; Fri, 9 Feb 2018 17:04:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5AFC12987F; Fri, 9 Feb 2018 17:04:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D261F2994D for ; Fri, 9 Feb 2018 17:04:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=TUuyXosmm7iuXPi4I2UrzuE/BvygqoX4etwmZ+8SpSI=; b=Uig5C1CdVXyBU/JK6yn27dXUp4 DRAlA7mxlALmKskj+NVef4/cOTVWxz/l6ePj21CDF/ZjJ6xC5cvI9mIwfH+fIw5LUexycV1EAsK8m VJNd/e5XDnn67zG4y46RQFc/znjeLs6RXcVnTYHHp3/uFrqd9VJ/+vE2+hu6aFp+SOU2bTKAVDadb ns2W+WkQ5lJVa5wdirt1J8y/SqK++y/Lcv8oOcWV0IuNzLao2Q3+1AB3H7zMFpCHN/VyembUu4s8n PCS1hKSov6UNc8ROy7UbyJBvc3+LdqFNRy79evsdqnIk74pCDbxc7JBNJsEbVE+an3IucpK4Xrsn3 uNF5dQiw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1ekC6S-0005FC-EE; Fri, 09 Feb 2018 17:04:48 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1ekC69-0004j9-8l for linux-arm-kernel@lists.infradead.org; Fri, 09 Feb 2018 17:04:31 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sre) with ESMTPSA id 9CC8F270544 From: Sebastian Reichel To: Shawn Guo , Sascha Hauer , Fabio Estevam , Will Deacon , Mark Rutland Subject: [PATCHv3 1/2] ARM: imx53: add secure-reg-access support for PMU Date: Fri, 9 Feb 2018 18:03:57 +0100 Message-Id: <20180209170358.7227-2-sebastian.reichel@collabora.co.uk> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180209170358.7227-1-sebastian.reichel@collabora.co.uk> References: <20180209170358.7227-1-sebastian.reichel@collabora.co.uk> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Russell King , Ian Ray , Nandor Han , Sebastian Reichel , kernel@collabora.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On i.MX53 it is necessary to set the DBG_EN bit in the platform GPC register to enable access to PMU counters other than the cycle counter. Signed-off-by: Sebastian Reichel --- arch/arm/mach-imx/mach-imx53.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 07c2e8dca494..661777ee1cc4 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -28,10 +28,49 @@ static void __init imx53_init_early(void) mxc_set_cpu_type(MXC_CPU_MX53); } +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 +#define GPC_DBG_EN BIT(16) + +/* + * This enables the DBGEN bit in ARM_GPC register, which is + * required for accessing some performance counter features. + * Technically it is only required while perf is used, but to + * keep the source code simple we just enable it all the time + * when the kernel configuration allows using the feature. + */ +static void imx53_pmu_init(void) +{ + void __iomem *gpc_reg; + struct device_node *node; + u32 gpc; + + if (!IS_ENABLED(CONFIG_ARM_PMU)) + return; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); + if (!node) + return; + + if (!of_property_read_bool(node, "secure-reg-access")) + return; + + gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4); + if (!gpc_reg) { + pr_warning("unable to map GPC to enable perf\n"); + return; + } + + gpc = __raw_readl(gpc_reg); + gpc |= GPC_DBG_EN; + __raw_writel(gpc, gpc_reg); + + return; +} + static void __init imx53_dt_init(void) { imx_src_init(); - + imx53_pmu_init(); imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); }