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Mon, 12 Feb 2018 06:29:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518416947; bh=mv4XUae3EQ7ny31orDnWv6LUWnwp4UKcpERMSTp1A44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NAvT2X7H+b9Tb3NlK+MfjDk55BRBuKYn25Mrl+a7B8KVqCqMIh1R5yPs+XUhF168G PfBBf5hLnXYVq7fz1OZpN4Z9P8fB6IysTezZ2Qb16WabNVsez3toyrteGBh7tgIjwG qwfHoEWJHKt9nPD00LU4ZJRaqg/fXI3e7cP98q2U= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3C99360F6D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: andy.gross@linaro.org Subject: [PATCH v3 3/3] arm64: dts: sdm845: Add serial console support Date: Mon, 12 Feb 2018 11:58:32 +0530 Message-Id: <20180212062832.2791-4-rnayak@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180212062832.2791-1-rnayak@codeaurora.org> References: <20180212062832.2791-1-rnayak@codeaurora.org> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, dianders@chromium.org, Rajendra Nayak , linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, evgreen@chromium.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the qup uart node and geni se instance needed to support the serial console on the MTP. Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 34 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 617c7bb25fb1..9eab2b815e0d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -10,4 +10,38 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp"; + + aliases { + serial0 = &qup_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&soc { + geni-se@ac0000 { + serial@a84000 { + status = "okay"; + }; + }; + + pinctrl@3400000 { + qup-uart2-default { + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup-uart2-sleep { + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 55a7e0b454e1..8cf8df25b06d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { interrupt-parent = <&intc>; @@ -193,6 +194,20 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qup_uart2_default: qup-uart2-default { + pinmux { + function = "qup9"; + pins = "gpio4", "gpio5"; + }; + }; + + qup_uart2_sleep: qup-uart2-sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + }; }; timer@17c90000 { @@ -271,5 +286,29 @@ #interrupt-cells = <4>; cell-index = <0>; }; + + qup_1: geni-se@ac0000 { + compatible = "qcom,geni-se-qup"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xac0000 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + + qup_uart2: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se-phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-1 = <&qup_uart2_sleep>; + interrupts = ; + status = "disabled"; + }; + }; }; };