| Message ID | 20180219151252.29289-1-marcel@ziswiler.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Marcel, Am Montag, 19. Februar 2018, 16:12:52 CEST schrieb Marcel Ziswiler: > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > Since commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting > during registration") ULPI has been broken on Tegra20 leading to the > following error message during boot: > > [ 1.974698] ulpi_phy_power_on: ulpi write failed > [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy > [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error -110 > > Debugging through the changes and finally also consulting the TRM > revealed that rather than the CDEV2 clock off OSC requiring such pin > muxing actually the PLL_P_OUT4 clock is in use. It looks like so far it > just worked by chance of that one having been enabled which Stephen's > commit now changed when reparenting sclk away from pll_p_out4 leaving > that one disabled. Fix this by properly assigning the PLL_P_OUT4 clock > as the ULPI PHY clock. I booted 4.17-rc1 (which includes this fix) on an AC100 (T20 paz00 board) and the error above is still there. Surprisingly the error vanishes when I revert your patch. So this patch actually *causes* the problem above on my board. Could it be, that we need all four clocks? Dimitry mentioned on IRC that it could also be a problem in the clock init table. I don't have the technical background myself to fix it, but I still wonder what could be so different between TrimSlice and AC100. Marc > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > > --- > > arch/arm/boot/dts/tegra20.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi > index 864a95872b8d..e05b6bb2599f 100644 > --- a/arch/arm/boot/dts/tegra20.dtsi > +++ b/arch/arm/boot/dts/tegra20.dtsi > @@ -741,7 +741,7 @@ > phy_type = "ulpi"; > clocks = <&tegra_car TEGRA20_CLK_USB2>, > <&tegra_car TEGRA20_CLK_PLL_U>, > - <&tegra_car TEGRA20_CLK_CDEV2>; > + <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; > clock-names = "reg", "pll_u", "ulpi-link"; > resets = <&tegra_car 58>, <&tegra_car 22>; > reset-names = "usb", "utmi-pads";
Hi Marc On Fri, 2018-04-20 at 10:52 +0200, Marc Dietrich wrote: > > ... > I booted 4.17-rc1 (which includes this fix) on an AC100 (T20 paz00 > board) and > the error above is still there. Surprisingly the error vanishes when > I revert > your patch. So this patch actually *causes* the problem above on my > board. That's really strange. I believe I do have one of them paz00 boards laying around somewhere as well. Just need to dig it out again and will give it a try. Looking at their schematics at least reveals the exact same circuit as found on all other T20 based boards using DAP_MCLK2 as REFCLK to the USB3315C which BTW is 24 MHz and not 26 MHz as CDEV2 claims! > Could it be, that we need all four clocks? Dimitry mentioned on IRC > that it > could also be a problem in the clock init table. I don't have the > technical > background myself to fix it, but I still wonder what could be so > different > between TrimSlice and AC100. I am wondering the same. However I still suspect that something is completely wrong in that area as that CDEV2 clock is completely bogus. It really does not exist! > Marc Cheers Marcel
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 864a95872b8d..e05b6bb2599f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -741,7 +741,7 @@ phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CDEV2>; + <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads";