From patchwork Fri Feb 23 12:25:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10237525 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8C0D660209 for ; Fri, 23 Feb 2018 12:28:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 771EE29536 for ; Fri, 23 Feb 2018 12:28:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B5E529550; Fri, 23 Feb 2018 12:28:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D099929556 for ; Fri, 23 Feb 2018 12:28:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=0wdoOMVzd7lA0q/Xvr/hL7SEvo2OtOeW+AHWeBRmBsU=; b=sddvGADZTDKmeFnyv6YtdrH2HU ogko6pEGJf+a1sS4vRZWqPrOXeGg/G51G3DGjpMzG3luKpm2MuORAx7TWxiPipdpCbUj5R+JoiwKR YlYx35R6dcwBrtDQwb5nHCfUsZTp08RFbd+guEF3zc1tIiTh6f4qPDy0CGHLxxEn3hW//Cp4S6oR4 q5glfA+pQJectVNzSNVxZGAvEWz/bpfhoHV3R0yMvDz6EXxUlm1bMsv2YYxBYvfuDhxL4HmqGVL2I xfBM2muwMX0N6Ntg3QvLNAadnkoEMAY6duNe4q8d94JC8fQ/C/w/Q6IsK0YChhetkQzqFs+yYC+yQ 1W/ytbgw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1epCSm-0003BM-9N; Fri, 23 Feb 2018 12:28:32 +0000 Received: from caracal.ash.relay.mailchannels.net ([23.83.222.30]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1epCS2-0002ga-ML for linux-arm-kernel@lists.infradead.org; Fri, 23 Feb 2018 12:27:55 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 1FB383E1CCF; Fri, 23 Feb 2018 12:27:31 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.14.37]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id 434D33E1C4B; Fri, 23 Feb 2018 12:27:30 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.18.41.110]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.13.1); Fri, 23 Feb 2018 12:27:31 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Whistle-Gusty: 27b247974c5e05d8_1519388850924_1647047744 X-MC-Loop-Signature: 1519388850924:92669367 X-MC-Ingress-Time: 1519388850924 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 9549F571E2; Fri, 23 Feb 2018 12:27:25 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Linus Walleij Subject: [PATCH v3 2/7] pinctrl: sunxi: support pin controllers with holes among IRQ banks Date: Fri, 23 Feb 2018 20:25:47 +0800 Message-Id: <20180223122552.58049-3-icenowy@aosc.io> In-Reply-To: <20180223122552.58049-1-icenowy@aosc.io> References: <20180223122552.58049-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180223_042747_646768_CF961630 X-CRM114-Status: GOOD ( 12.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. This situation cannot be processed with the current pinctrl IRQ code, as it only expects a offset to all IRQ banks. Update the code to use a logical IRQ bank to hardware IRQ bank map, so the new situation in H6 main pin controller can be processed. The old special situation which uses a constant offset (on A33 and V3s, both with a offset of 1) can be also processed with the new code. Signed-off-by: Icenowy Zheng --- Changes in v3: - change for the refactor in the new PATCH 1. No changes in v2. drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 4 +++- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 4 +++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 29 +++++++++++++++++------------ 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index da387211a75e..f043afa1aac5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -481,11 +481,13 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = { SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ }; +static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 }; + static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { .pins = sun8i_a33_pins, .npins = ARRAY_SIZE(sun8i_a33_pins), .irq_banks = 2, - .irq_bank_base = 1, + .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map, .disable_strict_mode = true, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 496ba34e1f5f..6704ce8e5e3d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ }; +static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; + static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { .pins = sun8i_v3s_pins, .npins = ARRAY_SIZE(sun8i_v3s_pins), .irq_banks = 2, - .irq_bank_base = 1, + .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, .irq_read_needs_mux = true }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 909ca1504b61..36502cbef6c2 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -110,7 +110,7 @@ struct sunxi_pinctrl_desc { int npins; unsigned pin_base; unsigned irq_banks; - unsigned irq_bank_base; + const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; }; @@ -263,14 +263,23 @@ static inline u32 sunxi_pull_offset(u16 pin) return pin_num * PULL_PINS_BITS; } +static inline u32 sunxi_irq_hw_bank_num(u8 bank, + const struct sunxi_pinctrl_desc *desc) +{ + if (!desc->irq_bank_map) + return bank; + else + return desc->irq_bank_map[bank]; +} + static inline u32 sunxi_irq_cfg_reg(u16 irq, const struct sunxi_pinctrl_desc *desc) { - unsigned bank_base = desc->irq_bank_base; u8 bank = irq / IRQ_PER_BANK; u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; - return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg; + return IRQ_CFG_REG + + sunxi_irq_hw_bank_num(bank, desc) * IRQ_MEM_SIZE + reg; } static inline u32 sunxi_irq_cfg_offset(u16 irq) @@ -282,9 +291,7 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq) static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, const struct sunxi_pinctrl_desc *desc) { - unsigned bank_base = desc->irq_bank_base; - - return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; + return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(bank, desc) * IRQ_MEM_SIZE; } static inline u32 sunxi_irq_ctrl_reg(u16 irq, @@ -304,17 +311,15 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq) static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, const struct sunxi_pinctrl_desc *desc) { - unsigned bank_base = desc->irq_bank_base; - - return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE; + return IRQ_DEBOUNCE_REG + + sunxi_irq_hw_bank_num(bank, desc) * IRQ_MEM_SIZE; } static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, const struct sunxi_pinctrl_desc *desc) { - unsigned bank_base = desc->irq_bank_base; - - return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; + return IRQ_STATUS_REG + + sunxi_irq_hw_bank_num(bank, desc) * IRQ_MEM_SIZE; } static inline u32 sunxi_irq_status_reg(u16 irq,