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[176.122.172.82]) by smtp.gmail.com with ESMTPSA id c7sm1961752pfg.36.2018.03.09.01.11.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 01:12:04 -0800 (PST) From: Alex Shi To: Marc Zyngier , Will Deacon , Ard Biesheuvel , Catalin Marinas , broonie@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 34/39] arm64: KVM: Add SMCCC_ARCH_WORKAROUND_1 fast handling Date: Fri, 9 Mar 2018 17:07:17 +0800 Message-Id: <20180309090722.26279-35-alex.shi@linaro.org> X-Mailer: git-send-email 2.16.2.440.gc6284da In-Reply-To: <20180309090722.26279-1-alex.shi@linaro.org> References: <20180309090722.26279-1-alex.shi@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180309_041216_971643_65E96071 X-CRM114-Status: GOOD ( 15.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Shi MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marc Zyngier commit f72af90c3783 upstream. Rewrite the patch on arch/arm64/kvm/hyp.S instead of arch/arm64/kvm/hyp/hyp-entry.S. We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible. So let's intercept it as early as we can by testing for the function call number as soon as we've identified a HVC call coming from the guest. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Alex Shi --- arch/arm64/kvm/hyp.S | 20 ++++++++++++++++++-- include/linux/arm-smccc.h | 6 +++--- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 86c289832272..525da4446f1c 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -974,10 +975,11 @@ el1_sync: // Guest trapped into EL2 lsr x2, x1, #ESR_ELx_EC_SHIFT cmp x2, #ESR_ELx_EC_HVC64 + ccmp x2, #ESR_ELx_EC_HVC32, #4, ne b.ne el1_trap - mrs x3, vttbr_el2 // If vttbr is valid, the 64bit guest - cbnz x3, el1_trap // called HVC + mrs x3, vttbr_el2 // If vttbr is valid, the guest + cbnz x3, el1_hvc_guest // called HVC /* Here, we're pretty sure the host called HVC. */ pop x2, x3 @@ -1003,6 +1005,20 @@ el1_sync: // Guest trapped into EL2 pop lr, xzr 2: eret +el1_hvc_guest: + /* + * Fastest possible path for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the host, + * so let's quickly get back to the guest. We don't bother + * restoring x3, as it can be clobbered anyway. + */ + ldr x3, [sp] // Guest's x0 + eor w3, w3, #ARM_SMCCC_ARCH_WORKAROUND_1 + cbnz w3, el1_trap + mov x0, x3 + add sp, sp, #16 + eret + el1_trap: /* * x1: ESR diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index a5ed4511af47..e7a439454950 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -57,9 +57,6 @@ #define ARM_SMCCC_OWNER_TRUSTED_OS 50 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 -#ifndef __ASSEMBLY__ -#include -#include #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ @@ -81,6 +78,9 @@ ARM_SMCCC_SMC_32, \ 0, 0x8000) +#ifndef __ASSEMBLY__ +#include +#include /** * struct arm_smccc_res - Result from SMC/HVC call * @a0-a3 result values from registers 0 to 3