From patchwork Fri Mar 16 14:02:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10287343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 683D1601A0 for ; Fri, 16 Mar 2018 14:04:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5715F28EE1 for ; Fri, 16 Mar 2018 14:04:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 497ED28EE7; Fri, 16 Mar 2018 14:04:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2426C28EE1 for ; Fri, 16 Mar 2018 14:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=oTXoJto0KZ0xiQN/ic5FUR8HHZbsUHd8ljqZvuz8K7I=; b=FZrYslo57svVhr0vn7FBfdPE8E 289KHCOsmPmfCv3pdmflwHGyy2tAZB8zKi/MDMGcFg7pHBMLCfMjYFiOWCFUC8lkkqoBNAiMypKwT NIWSrC1PROeDjcFUwP8TBwC9XepKjMqc3MB0dTBNGU2dOWfNQvtA2n2uw2c7smSGKLspS9M6P+6Pi mDV7MLD+X9De4Iipbe+blmv1mlactpTCDNEGun0IEUfb6STXQ4eTkBIKtgMcnlXVNFilnFd/DHiq3 m87QlchF11nlU7AAQfBiTKkhz4XKs1e1xUULlGISaz1gczSTUREy4LVnh3DAAeSbd4XYZn1XDmB8Z N/RfpBGQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ewpxn-00019a-Pv; Fri, 16 Mar 2018 14:04:07 +0000 Received: from glow.birch.relay.mailchannels.net ([23.83.209.71]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ewpxj-00018P-17 for linux-arm-kernel@lists.infradead.org; Fri, 16 Mar 2018 14:04:05 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id BA881120218; Fri, 16 Mar 2018 14:03:48 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.33.5]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id CAF221210CC; Fri, 16 Mar 2018 14:03:47 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.18.50.112]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.14.1); Fri, 16 Mar 2018 14:03:48 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Reaction-Juvenile: 08d8c5cf17b7ca50_1521209028554_2641613803 X-MC-Loop-Signature: 1521209028554:2624888046 X-MC-Ingress-Time: 1521209028554 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id AA8F859788; Fri, 16 Mar 2018 14:03:40 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Subject: [PATCH v4 1/9] pinctrl: sunxi: refactor irq related register function to have desc Date: Fri, 16 Mar 2018 22:02:07 +0800 Message-Id: <20180316140215.28663-2-icenowy@aosc.io> In-Reply-To: <20180316140215.28663-1-icenowy@aosc.io> References: <20180316140215.28663-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180316_070403_319631_A19D412D X-CRM114-Status: GOOD ( 15.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- Changes in v4: - Adjusted parameter sequence. Patch introduced in v3. drivers/pinctrl/sunxi/pinctrl-sunxi.c | 22 ++++++++++------------ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 26 ++++++++++++++++++-------- 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 341312d66512..af7264654151 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -835,7 +835,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base); + u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); u8 index = sunxi_irq_cfg_offset(d->hwirq); unsigned long flags; u32 regval; @@ -882,8 +882,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) static void sunxi_pinctrl_irq_ack(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 status_reg = sunxi_irq_status_reg(d->hwirq, - pctl->desc->irq_bank_base); + u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); u8 status_idx = sunxi_irq_status_offset(d->hwirq); /* Clear the IRQ */ @@ -893,7 +892,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d) static void sunxi_pinctrl_irq_mask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); + u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -910,7 +909,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d) static void sunxi_pinctrl_irq_unmask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); + u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -1002,7 +1001,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) if (bank == pctl->desc->irq_banks) return; - reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base); + reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); if (val) { @@ -1234,8 +1233,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, writel(src | div << 4, pctl->membase + - sunxi_irq_debounce_reg_from_bank(i, - pctl->desc->irq_bank_base)); + sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); } return 0; @@ -1410,11 +1408,11 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, for (i = 0; i < pctl->desc->irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ - writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i, - pctl->desc->irq_bank_base)); + writel(0, pctl->membase + + sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); writel(0xffffffff, - pctl->membase + sunxi_irq_status_reg_from_bank(i, - pctl->desc->irq_bank_base)); + pctl->membase + + sunxi_irq_status_reg_from_bank(pctl->desc, i)); irq_set_chained_handler_and_data(pctl->irq[i], sunxi_pinctrl_irq_handler, diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 11b128f54ed2..a13bd57d880d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -263,8 +263,10 @@ static inline u32 sunxi_pull_offset(u16 pin) return pin_num * PULL_PINS_BITS; } -static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base) +static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, + u16 irq) { + unsigned bank_base = desc->irq_bank_base; u8 bank = irq / IRQ_PER_BANK; u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; @@ -277,16 +279,19 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq) return irq_num * IRQ_CFG_IRQ_BITS; } -static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base) +static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) { + unsigned bank_base = desc->irq_bank_base; + return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; } -static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base) +static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, + u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_ctrl_reg_from_bank(bank, bank_base); + return sunxi_irq_ctrl_reg_from_bank(desc, bank); } static inline u32 sunxi_irq_ctrl_offset(u16 irq) @@ -295,21 +300,26 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq) return irq_num * IRQ_CTRL_IRQ_BITS; } -static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base) +static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) { + unsigned bank_base = desc->irq_bank_base; + return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE; } -static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base) +static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) { + unsigned bank_base = desc->irq_bank_base; + return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; } -static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base) +static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, + u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_status_reg_from_bank(bank, bank_base); + return sunxi_irq_status_reg_from_bank(desc, bank); } static inline u32 sunxi_irq_status_offset(u16 irq)