diff mbox

[2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

Message ID 20180316175354.21437-3-icenowy@aosc.io (mailing list archive)
State New, archived
Headers show

Commit Message

Icenowy Zheng March 16, 2018, 5:53 p.m. UTC
All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC to
be claimed, otherwise the whole DE2 space is inaccessible.

Add a device tree binding of the DE2 part as a sub-bus.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 .../devicetree/bindings/bus/sun50i-de2-bus.txt     | 37 ++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt

Comments

Maxime Ripard March 20, 2018, 6:46 p.m. UTC | #1
On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC to
> be claimed, otherwise the whole DE2 space is inaccessible.
> 
> Add a device tree binding of the DE2 part as a sub-bus.

Where did you get the info that it was a bus?

Maxime
Icenowy Zheng March 21, 2018, 2:18 a.m. UTC | #2
于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard <maxime.ripard@bootlin.com> 写到:
>On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
>> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC
>to
>> be claimed, otherwise the whole DE2 space is inaccessible.
>> 
>> Add a device tree binding of the DE2 part as a sub-bus.
>
>Where did you get the info that it was a bus?

There's no direct evidence, just some guess.

The DE2 is a whole part that is just allocated a memory
space at the user manual, and the SRAM controls the
access to all modules in the DE2.

So it might be a bus.

Implement it as a bus is a clear representation on A64.

>
>Maxime
Jernej Škrabec March 21, 2018, 5:13 p.m. UTC | #3
Hi all,

Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard <maxime.ripard@bootlin.com> 
写到:
> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC
> >
> >to
> >
> >> be claimed, otherwise the whole DE2 space is inaccessible.
> >> 
> >> Add a device tree binding of the DE2 part as a sub-bus.
> >
> >Where did you get the info that it was a bus?
> 
> There's no direct evidence, just some guess.
> 
> The DE2 is a whole part that is just allocated a memory
> space at the user manual, and the SRAM controls the
> access to all modules in the DE2.
> 
> So it might be a bus.
> 
> Implement it as a bus is a clear representation on A64.

Since there is already syscon for same mmio region, we migh as well use it 
when loading ccu-sun8i-de2 driver on A64.

Other options, like SRAM driver or bus driver, might better represent HW, but 
then we would have two DT nodes covering same mmio region, which I think is 
not really acceptable.

Any suggestions?

BTW, H6 has same design in this regard.

Best regards,
Jernej
Icenowy Zheng March 22, 2018, 6:08 a.m. UTC | #4
于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" <jernej.skrabec@siol.net> 写到:
>Hi all,
>
>Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
>> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
><maxime.ripard@bootlin.com> 
>写到:
>> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
>> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
>SoC
>> >
>> >to
>> >
>> >> be claimed, otherwise the whole DE2 space is inaccessible.
>> >> 
>> >> Add a device tree binding of the DE2 part as a sub-bus.
>> >
>> >Where did you get the info that it was a bus?
>> 
>> There's no direct evidence, just some guess.
>> 
>> The DE2 is a whole part that is just allocated a memory
>> space at the user manual, and the SRAM controls the
>> access to all modules in the DE2.
>> 
>> So it might be a bus.
>> 
>> Implement it as a bus is a clear representation on A64.
>
>Since there is already syscon for same mmio region, we migh as well use
>it 
>when loading ccu-sun8i-de2 driver on A64.
>
>Other options, like SRAM driver or bus driver, might better represent
>HW, but 

I think the device tree should properly represent the HW,
it's a basic requirment.

>then we would have two DT nodes covering same mmio region, which I
>think is 
>not really acceptable.

It's acceptable, and DE2 is not the only user of SRAM controller so far.

VE will also need a SRAM region to be claimed.

>
>Any suggestions?
>
>BTW, H6 has same design in this regard.
>
>Best regards,
>Jernej
Rob Herring (Arm) March 26, 2018, 10:22 p.m. UTC | #5
On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote:
> 
> 
> 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" <jernej.skrabec@siol.net> 写到:
> >Hi all,
> >
> >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
> >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
> ><maxime.ripard@bootlin.com> 
> >写到:
> >> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
> >SoC
> >> >
> >> >to
> >> >
> >> >> be claimed, otherwise the whole DE2 space is inaccessible.
> >> >> 
> >> >> Add a device tree binding of the DE2 part as a sub-bus.
> >> >
> >> >Where did you get the info that it was a bus?
> >> 
> >> There's no direct evidence, just some guess.
> >> 
> >> The DE2 is a whole part that is just allocated a memory
> >> space at the user manual, and the SRAM controls the
> >> access to all modules in the DE2.
> >> 
> >> So it might be a bus.
> >> 
> >> Implement it as a bus is a clear representation on A64.
> >
> >Since there is already syscon for same mmio region, we migh as well use
> >it 
> >when loading ccu-sun8i-de2 driver on A64.
> >
> >Other options, like SRAM driver or bus driver, might better represent
> >HW, but 
> 
> I think the device tree should properly represent the HW,
> it's a basic requirment.
> 
> >then we would have two DT nodes covering same mmio region, which I
> >think is 
> >not really acceptable.
> 
> It's acceptable, and DE2 is not the only user of SRAM controller so far.

No, it's not acceptable. Don't create overlapping mmio regions in DT.

> 
> VE will also need a SRAM region to be claimed.
> 
> >
> >Any suggestions?
> >
> >BTW, H6 has same design in this regard.
> >
> >Best regards,
> >Jernej
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
Icenowy Zheng March 26, 2018, 11:31 p.m. UTC | #6
于 2018年3月27日 GMT+08:00 上午6:22:58, Rob Herring <robh@kernel.org> 写到:
>On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote:
>> 
>> 
>> 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec"
><jernej.skrabec@siol.net> 写到:
>> >Hi all,
>> >
>> >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng
>napisal(a):
>> >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
>> ><maxime.ripard@bootlin.com> 
>> >写到:
>> >> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
>> >> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
>> >SoC
>> >> >
>> >> >to
>> >> >
>> >> >> be claimed, otherwise the whole DE2 space is inaccessible.
>> >> >> 
>> >> >> Add a device tree binding of the DE2 part as a sub-bus.
>> >> >
>> >> >Where did you get the info that it was a bus?
>> >> 
>> >> There's no direct evidence, just some guess.
>> >> 
>> >> The DE2 is a whole part that is just allocated a memory
>> >> space at the user manual, and the SRAM controls the
>> >> access to all modules in the DE2.
>> >> 
>> >> So it might be a bus.
>> >> 
>> >> Implement it as a bus is a clear representation on A64.
>> >
>> >Since there is already syscon for same mmio region, we migh as well
>use
>> >it 
>> >when loading ccu-sun8i-de2 driver on A64.
>> >
>> >Other options, like SRAM driver or bus driver, might better
>represent
>> >HW, but 
>> 
>> I think the device tree should properly represent the HW,
>> it's a basic requirment.
>> 
>> >then we would have two DT nodes covering same mmio region, which I
>> >think is 
>> >not really acceptable.
>> 
>> It's acceptable, and DE2 is not the only user of SRAM controller so
>far.
>
>No, it's not acceptable. Don't create overlapping mmio regions in DT.

Then should the SRAM controller driver be configured to take the syscon?

>
>> 
>> VE will also need a SRAM region to be claimed.
>> 
>> >
>> >Any suggestions?
>> >
>> >BTW, H6 has same design in this regard.
>> >
>> >Best regards,
>> >Jernej
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree"
>in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Maxime Ripard March 27, 2018, 8:11 a.m. UTC | #7
On Tue, Mar 27, 2018 at 07:31:18AM +0800, Icenowy Zheng wrote:
> 
> 
> 于 2018年3月27日 GMT+08:00 上午6:22:58, Rob Herring <robh@kernel.org> 写到:
> >On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote:
> >> 
> >> 
> >> 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec"
> ><jernej.skrabec@siol.net> 写到:
> >> >Hi all,
> >> >
> >> >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng
> >napisal(a):
> >> >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
> >> ><maxime.ripard@bootlin.com> 
> >> >写到:
> >> >> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> >> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
> >> >SoC
> >> >> >
> >> >> >to
> >> >> >
> >> >> >> be claimed, otherwise the whole DE2 space is inaccessible.
> >> >> >> 
> >> >> >> Add a device tree binding of the DE2 part as a sub-bus.
> >> >> >
> >> >> >Where did you get the info that it was a bus?
> >> >> 
> >> >> There's no direct evidence, just some guess.
> >> >> 
> >> >> The DE2 is a whole part that is just allocated a memory
> >> >> space at the user manual, and the SRAM controls the
> >> >> access to all modules in the DE2.
> >> >> 
> >> >> So it might be a bus.
> >> >> 
> >> >> Implement it as a bus is a clear representation on A64.
> >> >
> >> >Since there is already syscon for same mmio region, we migh as well
> >use
> >> >it 
> >> >when loading ccu-sun8i-de2 driver on A64.
> >> >
> >> >Other options, like SRAM driver or bus driver, might better
> >represent
> >> >HW, but 
> >> 
> >> I think the device tree should properly represent the HW,
> >> it's a basic requirment.
> >> 
> >> >then we would have two DT nodes covering same mmio region, which I
> >> >think is 
> >> >not really acceptable.
> >> 
> >> It's acceptable, and DE2 is not the only user of SRAM controller so
> >far.
> >
> >No, it's not acceptable. Don't create overlapping mmio regions in DT.
> 
> Then should the SRAM controller driver be configured to take the syscon?

We could have a single DT node that would export a syscon yes, just
like you did for the R40 ethernet case.

I'm not sure the SRAM controller itself needs to take the syscon, it
just can export its own.

Maxime
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
new file mode 100644
index 000000000000..87dfb33fb3be
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
@@ -0,0 +1,37 @@ 
+Device tree bindings for Allwinner A64 DE2 bus
+
+The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
+to be claimed for enabling the access.
+
+Required properties:
+
+ - compatible:		Should contain "allwinner,sun50i-a64-de2"
+ - reg:			A resource specifier for the register space
+ - #address-cells:	Must be set to 1
+ - #size-cells:		Must be set to 1
+ - ranges:		Must be set up to map the address space inside the
+			DE2, for the sub-blocks of DE2.
+ - allwinner,sram:	the SRAM that needs to be claimed
+
+Example:
+
+	de2@1000000 {
+		compatible = "allwinner,sun50i-a64-de2";
+		reg = <0x1000000 0x400000>;
+		allwinner,sram = <&de2_sram 1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1000000 0x400000>;
+
+		display_clocks: clock@0 {
+			compatible = "allwinner,sun50i-a64-de2-clk";
+			reg = <0x0 0x100000>;
+			clocks = <&ccu CLK_DE>,
+				 <&ccu CLK_BUS_DE>;
+			clock-names = "mod",
+				      "bus";
+			resets = <&ccu RST_BUS_DE>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+	};