From patchwork Mon Apr 2 12:04:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abbott Liu X-Patchwork-Id: 10319669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C19A660247 for ; Mon, 2 Apr 2018 12:27:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ADEA228A7A for ; Mon, 2 Apr 2018 12:27:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A1FD528AF7; Mon, 2 Apr 2018 12:27:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8352A28A7A for ; Mon, 2 Apr 2018 12:27:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KubJC3H3gdyZceEY9jML4emzppTcTVglDZqEEtRi0d0=; b=PAdpvN/MDsSorO U/fPFuMJ7sdM56NJghtgJeuwGnXKH1muzFBZWePU30+5Y91rYkncI75IhIs2XHT3xi0XuXoSNJoJW eY6wWx0EQa6j/FCqpTYs04dGfovQNTN64dv5Qr8aLvXe+mWLHu00SeRqps0JgF0ETigHWbgKVxwdG 6bTjgIGdgw5OUi35NQPxkA3LB34b96MFRX85vHSUv/yqtOjf61lLCpQzQzAatmqdz4/3Rs/94qO8X 7y0a74D/dLD/1nqk2LMeA2iP59StNn4Ckico3TsHpn4FITqxU9Hl1bDhG9sL/noOaCwIemxP5Vi3D sBfKW9C25KJ5fDwo2sIQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f2yYX-0006Rc-Bq; Mon, 02 Apr 2018 12:27:25 +0000 Received: from [45.249.212.35] (helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f2yWU-0004FE-Bs for linux-arm-kernel@lists.infradead.org; Mon, 02 Apr 2018 12:25:24 +0000 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6E1C2DCE4F9E8; Mon, 2 Apr 2018 20:24:59 +0800 (CST) Received: from linux.site (10.67.187.223) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.361.1; Mon, 2 Apr 2018 20:24:51 +0800 From: Abbott Liu To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 1/6] Add TTBR operator for kasan_init Date: Mon, 2 Apr 2018 20:04:35 +0800 Message-ID: <20180402120440.31900-2-liuwenliang@huawei.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20180402120440.31900-1-liuwenliang@huawei.com> References: <20180402120440.31900-1-liuwenliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.223] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180402_052518_777645_8C1A05FE X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The purpose of this patch is to provide set_ttbr0/get_ttbr0 to kasan_init function. The definitions of cp15 registers should be in arch/arm/include/asm/cp15.h rather than arch/arm/include/asm/kvm_hyp.h, so move them. Cc: Andrey Ryabinin Reviewed-by: Marc Zyngier Reviewed-by: Russell King - ARM Linux Reviewed-by: Christoffer Dall Acked-by: Mark Rutland Tested-by: Florian Fainelli Tested-by: Joel Stanley Tested-by: Abbott Liu Signed-off-by: Abbott Liu --- arch/arm/include/asm/cp15.h | 104 +++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/kvm_hyp.h | 52 --------------------- arch/arm/kvm/hyp/cp15-sr.c | 12 ++--- arch/arm/kvm/hyp/switch.c | 6 +-- 4 files changed, 113 insertions(+), 61 deletions(-) diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index 4c9fa72..99ebb31 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -3,6 +3,7 @@ #define __ASM_ARM_CP15_H #include +#include /* * CR1 bits (CP#15 CR1) @@ -65,8 +66,111 @@ #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) +#define TTBR0_32 __ACCESS_CP15(c2, 0, c0, 0) +#define TTBR1_32 __ACCESS_CP15(c2, 0, c0, 1) +#define PAR_32 __ACCESS_CP15(c7, 0, c4, 0) +#define TTBR0_64 __ACCESS_CP15_64(0, c2) +#define TTBR1_64 __ACCESS_CP15_64(1, c2) +#define PAR_64 __ACCESS_CP15_64(0, c7) +#define VTTBR __ACCESS_CP15_64(6, c2) +#define CNTV_CVAL __ACCESS_CP15_64(3, c14) +#define CNTVOFF __ACCESS_CP15_64(4, c14) + +#define MIDR __ACCESS_CP15(c0, 0, c0, 0) +#define CSSELR __ACCESS_CP15(c0, 2, c0, 0) +#define VPIDR __ACCESS_CP15(c0, 4, c0, 0) +#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5) +#define SCTLR __ACCESS_CP15(c1, 0, c0, 0) +#define CPACR __ACCESS_CP15(c1, 0, c0, 2) +#define HCR __ACCESS_CP15(c1, 4, c1, 0) +#define HDCR __ACCESS_CP15(c1, 4, c1, 1) +#define HCPTR __ACCESS_CP15(c1, 4, c1, 2) +#define HSTR __ACCESS_CP15(c1, 4, c1, 3) +#define TTBCR __ACCESS_CP15(c2, 0, c0, 2) +#define HTCR __ACCESS_CP15(c2, 4, c0, 2) +#define VTCR __ACCESS_CP15(c2, 4, c1, 2) +#define DACR __ACCESS_CP15(c3, 0, c0, 0) +#define DFSR __ACCESS_CP15(c5, 0, c0, 0) +#define IFSR __ACCESS_CP15(c5, 0, c0, 1) +#define ADFSR __ACCESS_CP15(c5, 0, c1, 0) +#define AIFSR __ACCESS_CP15(c5, 0, c1, 1) +#define HSR __ACCESS_CP15(c5, 4, c2, 0) +#define DFAR __ACCESS_CP15(c6, 0, c0, 0) +#define IFAR __ACCESS_CP15(c6, 0, c0, 2) +#define HDFAR __ACCESS_CP15(c6, 4, c0, 0) +#define HIFAR __ACCESS_CP15(c6, 4, c0, 2) +#define HPFAR __ACCESS_CP15(c6, 4, c0, 4) +#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0) +#define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6) +#define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1) +#define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0) +#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0) +#define TLBIALL __ACCESS_CP15(c8, 0, c7, 0) +#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4) +#define PRRR __ACCESS_CP15(c10, 0, c2, 0) +#define NMRR __ACCESS_CP15(c10, 0, c2, 1) +#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0) +#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1) +#define VBAR __ACCESS_CP15(c12, 0, c0, 0) +#define CID __ACCESS_CP15(c13, 0, c0, 1) +#define TID_URW __ACCESS_CP15(c13, 0, c0, 2) +#define TID_URO __ACCESS_CP15(c13, 0, c0, 3) +#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4) +#define HTPIDR __ACCESS_CP15(c13, 4, c0, 2) +#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0) +#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1) +#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0) + extern unsigned long cr_alignment; /* defined in entry-armv.S */ +static inline void set_par(u64 val) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + write_sysreg(val, PAR_64); + else + write_sysreg(val, PAR_32); +} + +static inline u64 get_par(void) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + return read_sysreg(PAR_64); + else + return read_sysreg(PAR_32); +} + +static inline void set_ttbr0(u64 val) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + write_sysreg(val, TTBR0_64); + else + write_sysreg(val, TTBR0_32); +} + +static inline u64 get_ttbr0(void) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + return read_sysreg(TTBR0_64); + else + return read_sysreg(TTBR0_32); +} + +static inline void set_ttbr1(u64 val) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + write_sysreg(val, TTBR1_64); + else + write_sysreg(val, TTBR1_32); +} + +static inline u64 get_ttbr1(void) +{ + if (IS_ENABLED(CONFIG_ARM_LPAE)) + return read_sysreg(TTBR1_64); + else + return read_sysreg(TTBR1_32); +} + static inline unsigned long get_cr(void) { unsigned long val; diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h index 1ab8329..8e8592e 100644 --- a/arch/arm/include/asm/kvm_hyp.h +++ b/arch/arm/include/asm/kvm_hyp.h @@ -36,58 +36,6 @@ __val; \ }) -#define TTBR0 __ACCESS_CP15_64(0, c2) -#define TTBR1 __ACCESS_CP15_64(1, c2) -#define VTTBR __ACCESS_CP15_64(6, c2) -#define PAR __ACCESS_CP15_64(0, c7) -#define CNTV_CVAL __ACCESS_CP15_64(3, c14) -#define CNTVOFF __ACCESS_CP15_64(4, c14) - -#define MIDR __ACCESS_CP15(c0, 0, c0, 0) -#define CSSELR __ACCESS_CP15(c0, 2, c0, 0) -#define VPIDR __ACCESS_CP15(c0, 4, c0, 0) -#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5) -#define SCTLR __ACCESS_CP15(c1, 0, c0, 0) -#define CPACR __ACCESS_CP15(c1, 0, c0, 2) -#define HCR __ACCESS_CP15(c1, 4, c1, 0) -#define HDCR __ACCESS_CP15(c1, 4, c1, 1) -#define HCPTR __ACCESS_CP15(c1, 4, c1, 2) -#define HSTR __ACCESS_CP15(c1, 4, c1, 3) -#define TTBCR __ACCESS_CP15(c2, 0, c0, 2) -#define HTCR __ACCESS_CP15(c2, 4, c0, 2) -#define VTCR __ACCESS_CP15(c2, 4, c1, 2) -#define DACR __ACCESS_CP15(c3, 0, c0, 0) -#define DFSR __ACCESS_CP15(c5, 0, c0, 0) -#define IFSR __ACCESS_CP15(c5, 0, c0, 1) -#define ADFSR __ACCESS_CP15(c5, 0, c1, 0) -#define AIFSR __ACCESS_CP15(c5, 0, c1, 1) -#define HSR __ACCESS_CP15(c5, 4, c2, 0) -#define DFAR __ACCESS_CP15(c6, 0, c0, 0) -#define IFAR __ACCESS_CP15(c6, 0, c0, 2) -#define HDFAR __ACCESS_CP15(c6, 4, c0, 0) -#define HIFAR __ACCESS_CP15(c6, 4, c0, 2) -#define HPFAR __ACCESS_CP15(c6, 4, c0, 4) -#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0) -#define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6) -#define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1) -#define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0) -#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0) -#define TLBIALL __ACCESS_CP15(c8, 0, c7, 0) -#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4) -#define PRRR __ACCESS_CP15(c10, 0, c2, 0) -#define NMRR __ACCESS_CP15(c10, 0, c2, 1) -#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0) -#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1) -#define VBAR __ACCESS_CP15(c12, 0, c0, 0) -#define CID __ACCESS_CP15(c13, 0, c0, 1) -#define TID_URW __ACCESS_CP15(c13, 0, c0, 2) -#define TID_URO __ACCESS_CP15(c13, 0, c0, 3) -#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4) -#define HTPIDR __ACCESS_CP15(c13, 4, c0, 2) -#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0) -#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1) -#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0) - #define VFP_FPEXC __ACCESS_VFP(FPEXC) /* AArch64 compatibility macros, only for the timer so far */ diff --git a/arch/arm/kvm/hyp/cp15-sr.c b/arch/arm/kvm/hyp/cp15-sr.c index c478281..d365e3c 100644 --- a/arch/arm/kvm/hyp/cp15-sr.c +++ b/arch/arm/kvm/hyp/cp15-sr.c @@ -31,8 +31,8 @@ void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt) ctxt->cp15[c0_CSSELR] = read_sysreg(CSSELR); ctxt->cp15[c1_SCTLR] = read_sysreg(SCTLR); ctxt->cp15[c1_CPACR] = read_sysreg(CPACR); - *cp15_64(ctxt, c2_TTBR0) = read_sysreg(TTBR0); - *cp15_64(ctxt, c2_TTBR1) = read_sysreg(TTBR1); + *cp15_64(ctxt, c2_TTBR0) = read_sysreg(TTBR0_64); + *cp15_64(ctxt, c2_TTBR1) = read_sysreg(TTBR1_64); ctxt->cp15[c2_TTBCR] = read_sysreg(TTBCR); ctxt->cp15[c3_DACR] = read_sysreg(DACR); ctxt->cp15[c5_DFSR] = read_sysreg(DFSR); @@ -41,7 +41,7 @@ void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt) ctxt->cp15[c5_AIFSR] = read_sysreg(AIFSR); ctxt->cp15[c6_DFAR] = read_sysreg(DFAR); ctxt->cp15[c6_IFAR] = read_sysreg(IFAR); - *cp15_64(ctxt, c7_PAR) = read_sysreg(PAR); + *cp15_64(ctxt, c7_PAR) = read_sysreg(PAR_64); ctxt->cp15[c10_PRRR] = read_sysreg(PRRR); ctxt->cp15[c10_NMRR] = read_sysreg(NMRR); ctxt->cp15[c10_AMAIR0] = read_sysreg(AMAIR0); @@ -60,8 +60,8 @@ void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt) write_sysreg(ctxt->cp15[c0_CSSELR], CSSELR); write_sysreg(ctxt->cp15[c1_SCTLR], SCTLR); write_sysreg(ctxt->cp15[c1_CPACR], CPACR); - write_sysreg(*cp15_64(ctxt, c2_TTBR0), TTBR0); - write_sysreg(*cp15_64(ctxt, c2_TTBR1), TTBR1); + write_sysreg(*cp15_64(ctxt, c2_TTBR0), TTBR0_64); + write_sysreg(*cp15_64(ctxt, c2_TTBR1), TTBR1_64); write_sysreg(ctxt->cp15[c2_TTBCR], TTBCR); write_sysreg(ctxt->cp15[c3_DACR], DACR); write_sysreg(ctxt->cp15[c5_DFSR], DFSR); @@ -70,7 +70,7 @@ void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt) write_sysreg(ctxt->cp15[c5_AIFSR], AIFSR); write_sysreg(ctxt->cp15[c6_DFAR], DFAR); write_sysreg(ctxt->cp15[c6_IFAR], IFAR); - write_sysreg(*cp15_64(ctxt, c7_PAR), PAR); + write_sysreg(*cp15_64(ctxt, c7_PAR), PAR_64); write_sysreg(ctxt->cp15[c10_PRRR], PRRR); write_sysreg(ctxt->cp15[c10_NMRR], NMRR); write_sysreg(ctxt->cp15[c10_AMAIR0], AMAIR0); diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c index ae45ae9..94d5bb9 100644 --- a/arch/arm/kvm/hyp/switch.c +++ b/arch/arm/kvm/hyp/switch.c @@ -134,12 +134,12 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu) if (!(hsr & HSR_DABT_S1PTW) && (hsr & HSR_FSC_TYPE) == FSC_PERM) { u64 par, tmp; - par = read_sysreg(PAR); + par = read_sysreg(PAR_64); write_sysreg(far, ATS1CPR); isb(); - tmp = read_sysreg(PAR); - write_sysreg(par, PAR); + tmp = read_sysreg(PAR_64); + write_sysreg(par, PAR_64); if (unlikely(tmp & 1)) return false; /* Translation failed, back to guest */