From patchwork Tue Apr 3 06:18:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Myl=C3=A8ne_Josserand?= X-Patchwork-Id: 10320649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 508C960532 for ; Tue, 3 Apr 2018 06:29:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 408BC287C0 for ; Tue, 3 Apr 2018 06:29:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3518E28984; Tue, 3 Apr 2018 06:29:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 83A61287C0 for ; Tue, 3 Apr 2018 06:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RMlVvIhTdAY/PaWVqBBqfLzfqhX9r8StUhkVCAZh8CY=; b=LVPWXF5gpwgaMs ocG05Nktw74re1G2BrG/3BasBH+xwX6jTry0SGNkkY6NStb1Vc8Ag/HlnQqHCPgm0/p4XsZIEplbY gHNZ3atWQ3lh43kdU+m2TXJ8sUb8FLEEz0g7qTrgV00kOcWGFQqKVDpPu7n86bb05pSWFjdAp2aeB fx08X9SESRM/Z5+ZMITw96LZ6MNoOc09dE6G8ko5wMuGsb7J5k5LiQZyQgsGi4IIQQfzli8+x0BTo fz3Zja6rPGjWofufR+X88icCt/CPB81Qt+QNR1qHvfdUYpBnaZAydKgqYERF3RAMXyoTfFLF9Ykg4 pZGw9dLKGO8jrsd+zftA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f3FRO-00031q-6W; Tue, 03 Apr 2018 06:29:10 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f3FJm-0005TO-1L for linux-arm-kernel@lists.infradead.org; Tue, 03 Apr 2018 06:21:23 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id D26E2207EA; Tue, 3 Apr 2018 08:20:59 +0200 (CEST) Received: from dell-desktop.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.bootlin.com (Postfix) with ESMTPSA id 7B9C820726; Tue, 3 Apr 2018 08:20:59 +0200 (CEST) From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org, marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org Subject: [PATCH v5 07/13] ARM: smp: Add initialization of CNTVOFF Date: Tue, 3 Apr 2018 08:18:30 +0200 Message-Id: <20180403061836.3926-8-mylene.josserand@bootlin.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180403061836.3926-1-mylene.josserand@bootlin.com> References: <20180403061836.3926-1-mylene.josserand@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180402_232118_585325_AD4FD7B3 X-CRM114-Status: GOOD ( 17.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, quentin.schulz@bootlin.com, linux-kernel@vger.kernel.org, clabbe.montjoie@gmail.com, thomas.petazzoni@bootlin.com, mylene.josserand@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The CNTVOFF register from arch timer is uninitialized. It should be done by the bootloader but it is currently not the case, even for boot CPU because this SoC is booting in secure mode. It leads to an random offset value meaning that each CPU will have a different time, which isn't working very well. Add assembly code used for boot CPU and secondary CPU cores to make sure that the CNTVOFF register is initialized. Because this code can be used by different platforms, add this assembly file in ARM's common folder. Signed-off-by: Mylène Josserand --- arch/arm/common/Makefile | 1 + arch/arm/common/smp_cntvoff.S | 35 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/smp_cntvoff.h | 8 ++++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm/common/smp_cntvoff.S create mode 100644 arch/arm/include/asm/smp_cntvoff.h diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 70b4a14ed993..83117deb86c8 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o +obj-$(CONFIG_SMP) += smp_cntvoff.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o CFLAGS_REMOVE_mcpm_entry.o = -pg diff --git a/arch/arm/common/smp_cntvoff.S b/arch/arm/common/smp_cntvoff.S new file mode 100644 index 000000000000..65ed199a50fe --- /dev/null +++ b/arch/arm/common/smp_cntvoff.S @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Chen-Yu Tsai + * Copyright (c) 2018 Bootlin + * + * Chen-Yu Tsai + * Mylène Josserand + * + * SMP support for sunxi based systems with Cortex A7/A15 + * + */ + +#include +#include + +ENTRY(smp_init_cntvoff) + .arch armv7-a + /* + * CNTVOFF has to be initialized either from non-secure Hypervisor + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled + * then it should be handled by the secure code + */ + cps #MON_MODE + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ + orr r0, r1, #1 + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ + isb + mov r0, #0 + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ + isb + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ + isb + cps #SVC_MODE + ret lr +ENDPROC(smp_init_cntvoff) diff --git a/arch/arm/include/asm/smp_cntvoff.h b/arch/arm/include/asm/smp_cntvoff.h new file mode 100644 index 000000000000..59a95f7604ee --- /dev/null +++ b/arch/arm/include/asm/smp_cntvoff.h @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __ASMARM_ARCH_CNTVOFF_H +#define __ASMARM_ARCH_CNTVOFF_H + +extern void smp_init_cntvoff(void); + +#endif