From patchwork Tue Apr 10 08:19:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10332509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 617676028A for ; Tue, 10 Apr 2018 08:18:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5541D28D26 for ; Tue, 10 Apr 2018 08:18:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4697528D28; Tue, 10 Apr 2018 08:18:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A6C3928D26 for ; Tue, 10 Apr 2018 08:18:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=OWgajPagijbHkffkwkspHajb99Mt1LYTTxKLcYyooy4=; b=kdh1JSCyi3LA+4 5yEBori9u1op/hgVKlhYVNQ6QzXWwyadbjjM35rUirlSy5lh8RVqvTXEcFP9BUVDL9uO05ens5Bre STFZOUvPA+LJs8hRRrmHr1Z6fk06ZOmm6YBCo6YQTUTSp3c+tcvTp5N8On0LniWF7kyD27kLmdmT9 ROBg/BHbcMx2bWXbhLNpsmwoD+fpqt/CNyUFhSPjBYC4YU1CvSQyxqk6XOuRlDkoC7T1nH6WPuh5x fFcqgcUjAELDJE9oac+3//qE2sFsv/f5gIgq/EkRN44Vmy2s2Pu0g6J8dojtb1xUa/m76mybewy10 RX1roBeYbVNlRnEqBPoQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f5oUG-0007od-IF; Tue, 10 Apr 2018 08:18:44 +0000 Received: from fllnx209.ext.ti.com ([198.47.19.16]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f5oUC-0007nI-TY; Tue, 10 Apr 2018 08:18:43 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3A8IPgs000386; Tue, 10 Apr 2018 03:18:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1523348305; bh=0ZSavutm3xUYXUAqah024bDHlzfa4/qc+62n2Sctl/I=; h=From:To:CC:Subject:Date; b=aJjtkhD/clQRecDp5kcNBL1g6zG9G6a251cA2Y+8Pxu6uKSXce5HXXqyhCTfCZKU+ 91OSeBiGM03A0D/ON3xILe/x7FKghowKc253jyvQPALmOQggf1c0QKxHIvCOOStK9f YhUbKTEeNiCw+HJ5+fTzLcAWkqyGuLGmZUwdkaEc= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3A8IPMp001703; Tue, 10 Apr 2018 03:18:25 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 10 Apr 2018 03:18:25 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 10 Apr 2018 03:18:25 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3A8ILvf011025; Tue, 10 Apr 2018 03:18:23 -0500 From: Vignesh R To: Marek Vasut Subject: [PATCH] mtd: spi-nor: cadence-quadspi: Add DMA support for direct mode reads Date: Tue, 10 Apr 2018 13:49:10 +0530 Message-ID: <20180410081910.858-1-vigneshr@ti.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180410_011841_090338_941B173A X-CRM114-Status: GOOD ( 20.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vignesh R , linux-kernel@vger.kernel.org, Boris Brezillon , linux-mtd@lists.infradead.org, Brian Norris , Linux ARM Mailing List Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to use DMA over memory mapped reads in direct mode. This helps in reducing CPU usage from ~100% to ~10% when reading data from flash. For non-DMA'able/vmalloc'd buffers, driver just falls back to CPU based memcpy. Signed-off-by: Vignesh R Reviewed-by: Marek Vasut --- drivers/mtd/spi-nor/cadence-quadspi.c | 96 ++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 4b8e9183489a..2f3a4d4232b3 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include #include @@ -73,6 +75,10 @@ struct cqspi_st { struct completion transfer_complete; struct mutex bus_mutex; + struct dma_chan *rx_chan; + struct completion rx_dma_complete; + dma_addr_t mmap_phys_base; + int current_cs; int current_page_size; int current_erase_size; @@ -915,11 +921,75 @@ static ssize_t cqspi_write(struct spi_nor *nor, loff_t to, return len; } +static void cqspi_rx_dma_callback(void *param) +{ + struct cqspi_st *cqspi = param; + + complete(&cqspi->rx_dma_complete); +} + +static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf, + loff_t from, size_t len) +{ + struct cqspi_flash_pdata *f_pdata = nor->priv; + struct cqspi_st *cqspi = f_pdata->cqspi; + enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; + int ret = 0; + struct dma_async_tx_descriptor *tx; + dma_cookie_t cookie; + dma_addr_t dma_dst; + + if (!cqspi->rx_chan || !virt_addr_valid(buf)) { + memcpy_fromio(buf, cqspi->ahb_base + from, len); + return 0; + } + + dma_dst = dma_map_single(nor->dev, buf, len, DMA_DEV_TO_MEM); + if (dma_mapping_error(nor->dev, dma_dst)) { + dev_err(nor->dev, "dma mapping failed\n"); + return -ENOMEM; + } + tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, + len, flags); + if (!tx) { + dev_err(nor->dev, "device_prep_dma_memcpy error\n"); + ret = -EIO; + goto err_unmap; + } + + tx->callback = cqspi_rx_dma_callback; + tx->callback_param = cqspi; + cookie = tx->tx_submit(tx); + reinit_completion(&cqspi->rx_dma_complete); + + ret = dma_submit_error(cookie); + if (ret) { + dev_err(nor->dev, "dma_submit_error %d\n", cookie); + ret = -EIO; + goto err_unmap; + } + + dma_async_issue_pending(cqspi->rx_chan); + ret = wait_for_completion_timeout(&cqspi->rx_dma_complete, + msecs_to_jiffies(len)); + if (ret <= 0) { + dmaengine_terminate_sync(cqspi->rx_chan); + dev_err(nor->dev, "DMA wait_for_completion_timeout\n"); + ret = -ETIMEDOUT; + goto err_unmap; + } + +err_unmap: + dma_unmap_single(nor->dev, dma_dst, len, DMA_DEV_TO_MEM); + + return 0; +} + static ssize_t cqspi_read(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; int ret; ret = cqspi_set_protocol(nor, 1); @@ -931,7 +1001,7 @@ static ssize_t cqspi_read(struct spi_nor *nor, loff_t from, return ret; if (f_pdata->use_direct_mode) - memcpy_fromio(buf, cqspi->ahb_base + from, len); + ret = cqspi_direct_read_execute(nor, buf, from, len); else ret = cqspi_indirect_read_execute(nor, buf, from, len); if (ret) @@ -1100,6 +1170,21 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) cqspi_controller_enable(cqspi, 1); } +static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) +{ + dma_cap_mask_t mask; + + dma_cap_zero(mask); + dma_cap_set(DMA_MEMCPY, mask); + + cqspi->rx_chan = dma_request_chan_by_mask(&mask); + if (IS_ERR(cqspi->rx_chan)) { + dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); + cqspi->rx_chan = NULL; + } + init_completion(&cqspi->rx_dma_complete); +} + static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) { const struct spi_nor_hwcaps hwcaps = { @@ -1177,6 +1262,9 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) f_pdata->use_direct_mode = true; dev_dbg(nor->dev, "using direct mode for %s\n", mtd->name); + + if (!cqspi->rx_chan) + cqspi_request_mmap_dma(cqspi); } } @@ -1237,6 +1325,7 @@ static int cqspi_probe(struct platform_device *pdev) dev_err(dev, "Cannot remap AHB address.\n"); return PTR_ERR(cqspi->ahb_base); } + cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; cqspi->ahb_size = resource_size(res_ahb); init_completion(&cqspi->transfer_complete); @@ -1307,6 +1396,9 @@ static int cqspi_remove(struct platform_device *pdev) cqspi_controller_enable(cqspi, 0); + if (cqspi->rx_chan) + dma_release_channel(cqspi->rx_chan); + clk_disable_unprepare(cqspi->clk); pm_runtime_put_sync(&pdev->dev);