diff mbox

[v2,6/8] spi: spi-s3c64xx: Fix indentation in the register offset definitions

Message ID 20180417142954.5507-6-s.nawrocki@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Sylwester Nawrocki April 17, 2018, 2:29 p.m. UTC
Change indentation so register address offset and register bit definitions
are aligned to same column.

Reviewed-by: Andi Shyti <andi@etezian.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 drivers/spi/spi-s3c64xx.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Comments

Mark Brown April 18, 2018, 10:47 a.m. UTC | #1
On Tue, Apr 17, 2018 at 04:29:52PM +0200, Sylwester Nawrocki wrote:
> Change indentation so register address offset and register bit definitions
> are aligned to same column.

This doesn't apply against current code, please check and resend.
Sylwester Nawrocki April 18, 2018, 12:17 p.m. UTC | #2
On 04/18/2018 12:47 PM, Mark Brown wrote:
> On Tue, Apr 17, 2018 at 04:29:52PM +0200, Sylwester Nawrocki wrote:
>> Change indentation so register address offset and register bit definitions
>> are aligned to same column.
>
> This doesn't apply against current code, please check and resend.

It seems there is no need to resend now as all patches from the series
are in your for-4.18 branch.
Mark Brown April 18, 2018, 1:49 p.m. UTC | #3
On Wed, Apr 18, 2018 at 02:17:36PM +0200, Sylwester Nawrocki wrote:
> On 04/18/2018 12:47 PM, Mark Brown wrote:

> > This doesn't apply against current code, please check and resend.

> It seems there is no need to resend now as all patches from the series
> are in your for-4.18 branch.

I applied a bunch of the series yesterday, it looks like something that
was applied then.
diff mbox

Patch

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b9b406138675..db33bc9b4147 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -28,15 +28,15 @@ 
 
 #define S3C64XX_SPI_CH_CFG		0x00
 #define S3C64XX_SPI_CLK_CFG		0x04
-#define S3C64XX_SPI_MODE_CFG	0x08
-#define S3C64XX_SPI_SLAVE_SEL	0x0C
+#define S3C64XX_SPI_MODE_CFG		0x08
+#define S3C64XX_SPI_SLAVE_SEL		0x0C
 #define S3C64XX_SPI_INT_EN		0x10
 #define S3C64XX_SPI_STATUS		0x14
 #define S3C64XX_SPI_TX_DATA		0x18
 #define S3C64XX_SPI_RX_DATA		0x1C
-#define S3C64XX_SPI_PACKET_CNT	0x20
-#define S3C64XX_SPI_PENDING_CLR	0x24
-#define S3C64XX_SPI_SWAP_CFG	0x28
+#define S3C64XX_SPI_PACKET_CNT		0x20
+#define S3C64XX_SPI_PENDING_CLR		0x24
+#define S3C64XX_SPI_SWAP_CFG		0x28
 #define S3C64XX_SPI_FB_CLK		0x2C
 
 #define S3C64XX_SPI_CH_HS_EN		(1<<6)	/* High Speed Enable */
@@ -77,9 +77,9 @@ 
 #define S3C64XX_SPI_INT_TX_FIFORDY_EN		(1<<0)
 
 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR		(1<<5)
-#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR	(1<<4)
+#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR		(1<<4)
 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR		(1<<3)
-#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR	(1<<2)
+#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR		(1<<2)
 #define S3C64XX_SPI_ST_RX_FIFORDY		(1<<1)
 #define S3C64XX_SPI_ST_TX_FIFORDY		(1<<0)
 
@@ -100,7 +100,7 @@ 
 #define S3C64XX_SPI_SWAP_TX_BIT			(1<<1)
 #define S3C64XX_SPI_SWAP_TX_EN			(1<<0)
 
-#define S3C64XX_SPI_FBCLK_MSK		(3<<0)
+#define S3C64XX_SPI_FBCLK_MSK			(3<<0)
 
 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \