| Message ID | 20180419071942.14828-2-sebastien.szymanski@armadeus.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 571ddd71cdba..530d5526b890 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -46,6 +46,25 @@ /* Delete UART8 in AIPS-1 (i.MX6UL specific) */ /delete-node/ &uart8; +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + / { soc { aips3: aips-bus@2200000 {
i.MX6ULL has different operating ranges than i.MX6UL so add the operating points for the i.MX6ULL. A 25mV offset is added to the minimum allowed values like for the i.MX6UL. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> --- Changes for v2: - Fix soc-operating-points voltage for 792MHz and 900MHz arch/arm/boot/dts/imx6ull.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)