| Message ID | 20180507113457.4716-1-nsekhar@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/07/2018 06:34 AM, Sekhar Nori wrote: > USB0 48MHz PHY clock registration fails on DA830 because the > da8xx-cfgchip clock driver cannot get a reference to USB0 > LPSC clock. > > The USB0 LPSC needs to be enabled during PHY clock enable. Setup > the clock lookup correctly to fix this. > > Signed-off-by: Sekhar Nori <nsekhar@ti.com> > --- > drivers/clk/davinci/psc-da830.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c > index f61abf5632ff..081b039fcb02 100644 > --- a/drivers/clk/davinci/psc-da830.c > +++ b/drivers/clk/davinci/psc-da830.c > @@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = { > .psc_init = &da830_psc0_init, > }; > > -LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx", > +LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", > + NULL, "musb-da8xx", > NULL, "cppi41-dmaengine"); > LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); > /* REVISIT: gpio-davinci.c should be modified to drop con_id */ > Reviewed-by: David Lechner <david@lechnology.com>
Quoting Sekhar Nori (2018-05-07 04:34:57) > USB0 48MHz PHY clock registration fails on DA830 because the > da8xx-cfgchip clock driver cannot get a reference to USB0 > LPSC clock. > > The USB0 LPSC needs to be enabled during PHY clock enable. Setup > the clock lookup correctly to fix this. > > Signed-off-by: Sekhar Nori <nsekhar@ti.com> > --- Applied to clk-next Did this need a fixes tag? And should it go into 4.17 final? Or it's not causing problems right now?
Hi Stephen, On Wednesday 16 May 2018 04:04 AM, Stephen Boyd wrote: > Quoting Sekhar Nori (2018-05-07 04:34:57) >> USB0 48MHz PHY clock registration fails on DA830 because the >> da8xx-cfgchip clock driver cannot get a reference to USB0 >> LPSC clock. >> >> The USB0 LPSC needs to be enabled during PHY clock enable. Setup >> the clock lookup correctly to fix this. >> >> Signed-off-by: Sekhar Nori <nsekhar@ti.com> >> --- > > Applied to clk-next > > Did this need a fixes tag? And should it go into 4.17 final? Or it's not > causing problems right now? We have not switched DaVinci to use common clock framework still. So no, this does not cause problems right now. All drivers/clk/davinci/* patches can be included for v4.18. Although if you are sending a v4.17 pull request to Linus anyway, and can include this, I would not mind it ;) We don't need stable backports definitely, so no need to add a Fixes: tag. Thanks, Sekhar
Hi Stephen, On Wednesday 16 May 2018 10:44 AM, Sekhar Nori wrote: > Hi Stephen, > > On Wednesday 16 May 2018 04:04 AM, Stephen Boyd wrote: >> Quoting Sekhar Nori (2018-05-07 04:34:57) >>> USB0 48MHz PHY clock registration fails on DA830 because the >>> da8xx-cfgchip clock driver cannot get a reference to USB0 >>> LPSC clock. >>> >>> The USB0 LPSC needs to be enabled during PHY clock enable. Setup >>> the clock lookup correctly to fix this. >>> >>> Signed-off-by: Sekhar Nori <nsekhar@ti.com> >>> --- >> >> Applied to clk-next >> >> Did this need a fixes tag? And should it go into 4.17 final? Or it's not >> causing problems right now? > > We have not switched DaVinci to use common clock framework still. So no, > this does not cause problems right now. All drivers/clk/davinci/* > patches can be included for v4.18. There are some more patches (fixes) to drivers/clk/davinci which have been reviewed and both David and I think are ready for merge[1]. Do you have them in your queue? Else, I can send a pull request for you to take a look and merge. Thanks, Sekhar [1] clk: davinci: psc-dm365: fix few clocks clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups clk: davinci: pll-dm355: fix SYSCLKn parent names clk: davinci: pll-dm355: drop pll2_sysclk2
diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c index f61abf5632ff..081b039fcb02 100644 --- a/drivers/clk/davinci/psc-da830.c +++ b/drivers/clk/davinci/psc-da830.c @@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = { .psc_init = &da830_psc0_init, }; -LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx", +LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", + NULL, "musb-da8xx", NULL, "cppi41-dmaengine"); LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); /* REVISIT: gpio-davinci.c should be modified to drop con_id */
USB0 48MHz PHY clock registration fails on DA830 because the da8xx-cfgchip clock driver cannot get a reference to USB0 LPSC clock. The USB0 LPSC needs to be enabled during PHY clock enable. Setup the clock lookup correctly to fix this. Signed-off-by: Sekhar Nori <nsekhar@ti.com> --- drivers/clk/davinci/psc-da830.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)