| Message ID | 20180509172606.29387-3-david@lechnology.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wednesday 09 May 2018 10:55 PM, David Lechner wrote: > +void of_da850_pll0_init(struct device_node *node) > { > - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, > - &da850_pll0_obsclk_info, > - da850_pll0_sysclk_info, 7, base, cfgchip); > + void __iomem *base; > + struct regmap *cfgchip; > + > + base = of_iomap(node, 0); > + if (!base) { > + pr_err("%s: ioremap failed\n", __func__); > + return; > + } > + > + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); It will be nice to handle the error case here. > + > + of_davinci_pll_init(NULL, node, &da850_pll0_info, > + &da850_pll0_obsclk_info, > + da850_pll0_sysclk_info, 7, base, cfgchip); Apart from that, it looks good to me. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Thanks, Sekhar
On 05/15/2018 08:31 AM, Sekhar Nori wrote: > On Wednesday 09 May 2018 10:55 PM, David Lechner wrote: >> +void of_da850_pll0_init(struct device_node *node) >> { >> - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, >> - &da850_pll0_obsclk_info, >> - da850_pll0_sysclk_info, 7, base, cfgchip); >> + void __iomem *base; >> + struct regmap *cfgchip; >> + >> + base = of_iomap(node, 0); >> + if (!base) { >> + pr_err("%s: ioremap failed\n", __func__); >> + return; >> + } >> + >> + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); In your previous review, you pointed out that the error did not need to be handled here because it is handled later in davinci_pll_clk_register(). We get a warning there because cfgchip is only needed for unlocking the PLL for CPU frequency scaling and is not critical for operation of the clocks. > > It will be nice to handle the error case here. > >> + >> + of_davinci_pll_init(NULL, node, &da850_pll0_info, >> + &da850_pll0_obsclk_info, >> + da850_pll0_sysclk_info, 7, base, cfgchip); > > Apart from that, it looks good to me. > > Reviewed-by: Sekhar Nori <nsekhar@ti.com> > > Thanks, > Sekhar >
On Tuesday 15 May 2018 09:12 PM, David Lechner wrote: > On 05/15/2018 08:31 AM, Sekhar Nori wrote: >> On Wednesday 09 May 2018 10:55 PM, David Lechner wrote: >>> +void of_da850_pll0_init(struct device_node *node) >>> { >>> - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, >>> - &da850_pll0_obsclk_info, >>> - da850_pll0_sysclk_info, 7, base, cfgchip); >>> + void __iomem *base; >>> + struct regmap *cfgchip; >>> + >>> + base = of_iomap(node, 0); >>> + if (!base) { >>> + pr_err("%s: ioremap failed\n", __func__); >>> + return; >>> + } >>> + >>> + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); > > In your previous review, you pointed out that the error did not need to > be handled here because it is handled later in davinci_pll_clk_register().> > We get a warning there because cfgchip is only needed for unlocking the > PLL for CPU frequency scaling and is not critical for operation of the > clocks. Oops, forgot about that :) Reviewed-by: Sekhar Nori <nsekhar@ti.com> Thanks, Sekhar
diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c index 00a6ece7b524..fde4642a993f 100644 --- a/drivers/clk/davinci/pll-da850.c +++ b/drivers/clk/davinci/pll-da850.c @@ -12,6 +12,8 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/mfd/da8xx-cfgchip.h> +#include <linux/mfd/syscon.h> +#include <linux/of_address.h> #include <linux/of.h> #include <linux/types.h> @@ -135,11 +137,22 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { NULL }; -int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) +void of_da850_pll0_init(struct device_node *node) { - return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info, - &da850_pll0_obsclk_info, - da850_pll0_sysclk_info, 7, base, cfgchip); + void __iomem *base; + struct regmap *cfgchip; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + + of_davinci_pll_init(NULL, node, &da850_pll0_info, + &da850_pll0_obsclk_info, + da850_pll0_sysclk_info, 7, base, cfgchip); } static const struct davinci_pll_clk_info da850_pll1_info = { diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c index f362f10d8459..dcfa780f828a 100644 --- a/drivers/clk/davinci/pll.c +++ b/drivers/clk/davinci/pll.c @@ -770,8 +770,10 @@ static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *de return pdata; } +/* needed in early boot for clocksource/clockevent */ +CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); + static const struct of_device_id davinci_pll_of_match[] = { - { .compatible = "ti,da850-pll0", .data = of_da850_pll0_init }, { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, { } }; diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h index 562652fc0759..b2e5c4496645 100644 --- a/drivers/clk/davinci/pll.h +++ b/drivers/clk/davinci/pll.h @@ -123,7 +123,7 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node, /* Platform-specific callbacks */ int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); +void of_da850_pll0_init(struct device_node *node); int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
PLL0 on davinci/da850-type device needs to be registered early in boot because it is needed for clocksource/clockevent. Change the driver to use CLK_OF_DECLARE for this special case. Signed-off-by: David Lechner <david@lechnology.com> --- v10 changes: - removed duplicate warning message v9 changes: - new patch in v9 drivers/clk/davinci/pll-da850.c | 21 +++++++++++++++++---- drivers/clk/davinci/pll.c | 4 +++- drivers/clk/davinci/pll.h | 2 +- 3 files changed, 21 insertions(+), 6 deletions(-)