From patchwork Thu May 10 16:23:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Capper X-Patchwork-Id: 10392087 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 755296053D for ; Thu, 10 May 2018 16:29:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66A2028B77 for ; Thu, 10 May 2018 16:29:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B7F828BD9; Thu, 10 May 2018 16:29:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B985F28B77 for ; Thu, 10 May 2018 16:29:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fv2FhTvhhw/UkEbnvMAjy4yze8D7Ib0ttFhU0UqdcfY=; b=cjFAMrOMWS8ANfUHrP6z3FptIt pQmoOOOxXhKyTxRz9HYCRnGurRZJxeE8KbAmFw5AehqPD+YmwppjigR6r3/JJS51fR80tj2kfTae2 9eFI4kGy5DOdidY3WuIFAzSrcRRrYG2fH1QSdX4BLU4ugJbi+S5sxVNMchzpAmvgDZZvCAI1NNRma RUeRfhyR5jZaBMmA3GJF4ZLW31ZKqTwtKLELJKk8ctfRq4hOm4NNEVg6272dq2sRx9TYNDe6Abfl8 XYGNt+B7blLWv/eq00WjXw27mX3fz69iE0SjMifRlr3XQVgWpnG0qm7XvmSDjnzhorcR9MLhHk/pm +yirJSeQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fGoRn-0006ef-5B; Thu, 10 May 2018 16:29:39 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fGoMh-00037Y-LX for linux-arm-kernel@lists.infradead.org; Thu, 10 May 2018 16:24:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A39EB15AB; Thu, 10 May 2018 09:24:16 -0700 (PDT) Received: from capper-debian.arm.com (unknown [10.37.12.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9846F3F73E; Thu, 10 May 2018 09:24:15 -0700 (PDT) From: Steve Capper To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com Subject: [PATCH v3 8/8] arm64: mm: Add 48/52-bit kernel VA support Date: Thu, 10 May 2018 17:23:47 +0100 Message-Id: <20180510162347.3858-9-steve.capper@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180510162347.3858-1-steve.capper@arm.com> References: <20180510162347.3858-1-steve.capper@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180510_092423_776993_8E4F7502 X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , ard.biesheuvel@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the option to use 52-bit VA support upon availability at boot. We use the same KASAN_SHADOW_OFFSET for both 48 and 52 bit VA spaces as in both cases the start and end of the KASAN shadow region are PGD aligned. From ID_AA64MMFR2, we check the LVA field on very early boot and set the VA size, PGDIR_SHIFT and TCR.T[01]SZ values which then influence how the rest of the memory system behaves. Note that userspace addresses will still be capped out at 48-bit. More patches are needed to deal with scenarios where the user provides MMAP_FIXED hint and a high address to mmap. Signed-off-by: Steve Capper --- arch/arm64/Kconfig | 10 +++++++++- arch/arm64/mm/proc.S | 13 +++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f68eeab08904..6fe0c2976f0d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -266,6 +266,7 @@ config PGTABLE_LEVELS default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 + default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_52 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 @@ -282,6 +283,7 @@ config MULTI_IRQ_HANDLER config KASAN_SHADOW_OFFSET hex depends on KASAN + default 0xdfffa00000000000 if ARM64_VA_BITS_52 default 0xdfffa00000000000 if ARM64_VA_BITS_48 default 0xdfffd00000000000 if ARM64_VA_BITS_47 default 0xdffffe8000000000 if ARM64_VA_BITS_42 @@ -670,6 +672,10 @@ config ARM64_VA_BITS_47 config ARM64_VA_BITS_48 bool "48-bit" +config ARM64_VA_BITS_52 + bool "52-bit (ARMv8.2) (48 if not in hardware)" + depends on ARM64_64K_PAGES + endchoice config ARM64_VA_BITS @@ -679,10 +685,12 @@ config ARM64_VA_BITS default 42 if ARM64_VA_BITS_42 default 47 if ARM64_VA_BITS_47 default 48 if ARM64_VA_BITS_48 + default 52 if ARM64_VA_BITS_52 config ARM64_VA_BITS_MIN int - default ARM64_VA_BITS + default ARM64_VA_BITS if !ARM64_VA_BITS_52 + default 48 if ARM64_VA_BITS_52 choice prompt "Physical address space size" diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 5f8d9e452190..031604502776 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -472,9 +472,22 @@ ENTRY(__cpu_setup) ENDPROC(__cpu_setup) ENTRY(__setup_va_constants) +#ifdef CONFIG_ARM64_VA_BITS_52 + mrs_s x5, SYS_ID_AA64MMFR2_EL1 + and x5, x5, #0xf << ID_AA64MMFR2_LVA_SHIFT + cmp x5, #1 << ID_AA64MMFR2_LVA_SHIFT + b.ne 1f + mov x0, #VA_BITS + mov x1, TCR_T0SZ(VA_BITS) + mov x2, #1 << (VA_BITS - PGDIR_SHIFT) + b 2f +#endif + +1: mov x0, #VA_BITS_MIN mov x1, TCR_T0SZ(VA_BITS_MIN) mov x2, #1 << (VA_BITS_MIN - PGDIR_SHIFT) +2: str_l x0, vabits_actual, x5 str_l x1, idmap_t0sz, x5 str_l x2, ptrs_per_pgd, x5