From patchwork Mon May 14 21:16:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 10399391 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AA6FD600D0 for ; Mon, 14 May 2018 21:27:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 113961FF62 for ; Mon, 14 May 2018 21:27:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 01D36283A5; Mon, 14 May 2018 21:27:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 16F551FF62 for ; Mon, 14 May 2018 21:27:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=pa2k4SGKZQXKvWdfhdLjVfNV15b5iPrNmC9GL+B6QRs=; b=cAIzjZLmLuqVZeOwJ/QH9arlKQ JPbYj4RV4sW2AcGoqovRO+fvaWsHAa2gdz+JZsUgKl/QaTiTN1xwu9Tj2DO8DhCYHoM/qT/ZFiM7X /fnUluZmTeGZNFtRyHOL5KhG3wHY3F75OZeFLtZ0UMXJ5B8hY/FlHv0DVUAX/RGKpPKZY8heDqDrY FjsyYr/ZY44gWg4yVD1utCETu9hmj+ZvU5At4LxSH1M47CmsadDLrkuG7Sn2ektztpUkASmBIqmRJ TkVC53xLPqCM1TDS7/kkXCAqx1GlL3onEZfhm7rDIAMombrTIBaxBFJ7RsN2cL1Q+t3QVPRjzA5LJ vHhYPiiw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fIL0U-0003fj-T1; Mon, 14 May 2018 21:27:46 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fIKq5-0002ut-JQ; Mon, 14 May 2018 21:17:08 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 81CD0263A2C From: Enric Balletbo i Serra To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Will Deacon , Heiko Stuebner , Michael Turquette , Stephen Boyd , Sandy Huang , David Airlie Subject: [RFC PATCH 09/10] arm64: dts: rk3399: Add dfi and dmc nodes. Date: Mon, 14 May 2018 23:16:09 +0200 Message-Id: <20180514211610.26618-10-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514211610.26618-1-enric.balletbo@collabora.com> References: <20180514211610.26618-1-enric.balletbo@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180514_141701_957174_C50BDE45 X-CRM114-Status: GOOD ( 15.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Shawn Lin , Kever Yang , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@collabora.com, linux-clk@vger.kernel.org, Brian Norris , linux-rockchip@lists.infradead.org, Nickey Yang , Jacob Chen , Caesar Wang , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Derek Basehore , Sean Paul , Mark Yao , linux-arm-kernel@lists.infradead.org, Lin Huang , Douglas Anderson , Yakir Yang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lin Huang These are required to support DDR DVFS on rk3399 platform. The patch also introduces two new files (rk3399-dram.h and rk3399-dram-default-timing) with default DRAM settings. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra --- .../rockchip/rk3399-dram-default-timing.dtsi | 38 ++++++++++ arch/arm64/boot/dts/rockchip/rk3399-dram.h | 73 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 29 ++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 +++++ 4 files changed, 160 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dram.h diff --git a/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi new file mode 100644 index 000000000000..4dfe3e1d8bdf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright (c) 2016-2018, Fuzhou Rockchip Electronics Co., Ltd + * + * Author: Lin Huang + */ + +#include "rk3399-dram.h" + +rockchip,ddr3_speed_bin = <21>; +rockchip,pd_idle = <0x40>; +rockchip,sr_idle = <0x2>; +rockchip,sr_mc_gate_idle = <0x3>; +rockchip,srpd_lite_idle = <0x4>; +rockchip,standby_idle = <0x2000>; +rockchip,dram_dll_dis_freq = <300000000>; +rockchip,phy_dll_dis_freq = <125000000>; +rockchip,auto_pd_dis_freq = <666000000>; +rockchip,ddr3_odt_dis_freq = <333000000>; +rockchip,ddr3_drv = ; +rockchip,ddr3_odt = ; +rockchip,phy_ddr3_ca_drv = ; +rockchip,phy_ddr3_dq_drv = ; +rockchip,phy_ddr3_odt = ; +rockchip,lpddr3_odt_dis_freq = <333000000>; +rockchip,lpddr3_drv = ; +rockchip,lpddr3_odt = ; +rockchip,phy_lpddr3_ca_drv = ; +rockchip,phy_lpddr3_dq_drv = ; +rockchip,phy_lpddr3_odt = ; +rockchip,lpddr4_odt_dis_freq = <333000000>; +rockchip,lpddr4_drv = ; +rockchip,lpddr4_dq_odt = ; +rockchip,lpddr4_ca_odt = ; +rockchip,phy_lpddr4_ca_drv = ; +rockchip,phy_lpddr4_ck_cs_drv = ; +rockchip,phy_lpddr4_dq_drv = ; +rockchip,phy_lpddr4_odt = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-dram.h b/arch/arm64/boot/dts/rockchip/rk3399-dram.h new file mode 100644 index 000000000000..4b3d4a79923b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-dram.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR X11) */ +/* + * Copyright (c) 2016-2018, Fuzhou Rockchip Electronics Co., Ltd + * + * Author: Lin Huang + */ + +#ifndef _DTS_DRAM_ROCKCHIP_RK3399_H +#define _DTS_DRAM_ROCKCHIP_RK3399_H + +#define DDR3_DS_34ohm 34 +#define DDR3_DS_40ohm 40 + +#define DDR3_ODT_DIS 0 +#define DDR3_ODT_40ohm 40 +#define DDR3_ODT_60ohm 60 +#define DDR3_ODT_120ohm 120 + +#define LP2_DS_34ohm 34 +#define LP2_DS_40ohm 40 +#define LP2_DS_48ohm 48 +#define LP2_DS_60ohm 60 +#define LP2_DS_68_6ohm 68 /* optional */ +#define LP2_DS_80ohm 80 +#define LP2_DS_120ohm 120 /* optional */ + +#define LP3_DS_34ohm 34 +#define LP3_DS_40ohm 40 +#define LP3_DS_48ohm 48 +#define LP3_DS_60ohm 60 +#define LP3_DS_80ohm 80 +#define LP3_DS_34D_40U 3440 +#define LP3_DS_40D_48U 4048 +#define LP3_DS_34D_48U 3448 + +#define LP3_ODT_DIS 0 +#define LP3_ODT_60ohm 60 +#define LP3_ODT_120ohm 120 +#define LP3_ODT_240ohm 240 + +#define LP4_PDDS_40ohm 40 +#define LP4_PDDS_48ohm 48 +#define LP4_PDDS_60ohm 60 +#define LP4_PDDS_80ohm 80 +#define LP4_PDDS_120ohm 120 +#define LP4_PDDS_240ohm 240 + +#define LP4_DQ_ODT_40ohm 40 +#define LP4_DQ_ODT_48ohm 48 +#define LP4_DQ_ODT_60ohm 60 +#define LP4_DQ_ODT_80ohm 80 +#define LP4_DQ_ODT_120ohm 120 +#define LP4_DQ_ODT_240ohm 240 +#define LP4_DQ_ODT_DIS 0 + +#define LP4_CA_ODT_40ohm 40 +#define LP4_CA_ODT_48ohm 48 +#define LP4_CA_ODT_60ohm 60 +#define LP4_CA_ODT_80ohm 80 +#define LP4_CA_ODT_120ohm 120 +#define LP4_CA_ODT_240ohm 240 +#define LP4_CA_ODT_DIS 0 + +#define PHY_DRV_ODT_Hi_Z 0 +#define PHY_DRV_ODT_240 240 +#define PHY_DRV_ODT_120 120 +#define PHY_DRV_ODT_80 80 +#define PHY_DRV_ODT_60 60 +#define PHY_DRV_ODT_48 48 +#define PHY_DRV_ODT_40 40 +#define PHY_DRV_ODT_34_3 34 + +#endif /* _DTS_DRAM_ROCKCHIP_RK3399_H */ diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index d8a120f945c8..4c634e58425d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -147,6 +147,31 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + }; + }; }; &cpu_l0 { @@ -176,3 +201,7 @@ &gpu { operating-points-v2 = <&gpu_opp_table>; }; + +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 4550c0f82be9..e012cc8ae3d4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1830,6 +1830,26 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + #include "rk3399-dram-default-timing.dtsi" + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>;