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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id v16-v6sm69610481pfk.164.2018.05.24.20.02.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 May 2018 20:02:14 -0700 (PDT) From: Andrey Smirnov To: Shawn Guo Subject: [PATCH] ARM: dts: imx51-zii-rdu1: Make sure SD1_WP is low Date: Thu, 24 May 2018 20:01:53 -0700 Message-Id: <20180525030153.15986-1-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.17.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180524_200226_555773_E2F1DF5E X-CRM114-Status: GOOD ( 14.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nikita Yushchenko , devicetree@vger.kernel.org, Andrey Smirnov , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Fabio Estevam , Chris Healy , Lucas Stach MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Make sure that MX51_PAD_GPIO1_1 does not remain configure as ALT0/SD1_WP (it is out of reset). This is needed because of external pull-up resistor attached to that pad that, when left unchanged, will drive SD1_WP high preventing eSDHC1/eMMC from working correctly. To fix that add a pinmux configuration line configureing the pad to function as a GPIO. While we are at it, add a corresponding input GPIO hog in an effort to minimize current consumption. Cc: Nikita Yushchenko Cc: Shawn Guo Cc: Fabio Estevam Cc: Lucas Stach Cc: Chris Healy Cc: Rob Herring Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index df9eca94d812..d484e7e46b27 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -476,6 +476,17 @@ status = "okay"; }; +&gpio1 { + unused-sd3-wp-gpio { + /* + * See pinctrl_esdhc1 below for more details on this + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; @@ -660,6 +671,23 @@ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + /* + * GPIO1_1 is not directly used by eSDHC1 in + * any capacity, but earlier versions of RDU1 + * used that pin as WP GPIO for eSDHC3 and + * because of that that pad has an external + * pull-up resistor. This is problematic + * because out of reset the pad is configured + * as ALT0 which serves as SD1_WP, which, when + * pulled high by and external pull-up, will + * inhibit execution of any write request to + * attached eMMC device. + * + * To avoid this problem we configure the pad + * to ALT1/GPIO and avoid driving SD1_WP + * signal high. + */ + MX51_PAD_GPIO1_1__GPIO1_1 0x0000 >; };