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[216.71.193.140]) by smtp.gmail.com with ESMTPSA id d22-v6sm11149949pfl.10.2018.05.31.23.29.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 May 2018 23:29:09 -0700 (PDT) From: Vasily Khoruzhick To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] dts: sunxi: A64: Add PWM controllers Date: Thu, 31 May 2018 23:29:00 -0700 Message-Id: <20180601062901.8052-3-anarsoul@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180601062901.8052-1-anarsoul@gmail.com> References: <20180601062901.8052-1-anarsoul@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180531_232921_257380_A4C40114 X-CRM114-Status: GOOD ( 14.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andre Przywara MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andre Przywara The Allwinner A64 SoC features two PWM controllers, which are fully compatible to the one used in the A13 and H3 chips. Add the nodes for the devices (one for the "normal" PWM, the other for the one in the CPUS domain) and the pins their outputs are connected to. On the A64 the "normal" PWM is muxed together with one of the MDIO pins used to communicate with the Ethernet PHY, so it won't be usable on many boards. But the Pinebook laptop uses this pin for controlling the LCD backlight. On Pine64 the CPUS PWM pin however is routed to the "RPi2" header, at the same location as the PWM pin on the RaspberryPi. [vasily: fixed comment message as requested by Stefan Bruens] Signed-off-by: Andre Przywara Tested-by: Vasily Khoruzhick on Pinebook (only the "normal" PWM) Tested-by: Harald Geyer on Teres-I (only the "normal" PWM) --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index b5e903ccf0ec..e94bfa8477f6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -365,6 +365,11 @@ bias-pull-up; }; + pwm_pin: pwm_pin { + pins = "PD22"; + function = "pwm"; + }; + rmii_pins: rmii_pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; @@ -630,6 +635,15 @@ #interrupt-cells = <3>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; @@ -667,6 +681,15 @@ #size-cells = <0>; }; + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01f03800 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -687,6 +710,11 @@ pins = "PL8", "PL9"; function = "s_i2c"; }; + + r_pwm_pin: pwm { + pins = "PL10"; + function = "s_pwm"; + }; }; r_rsb: rsb@1f03400 {