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[216.71.193.140]) by smtp.gmail.com with ESMTPSA id x2-v6sm9746352pfn.11.2018.06.05.22.17.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Jun 2018 22:17:26 -0700 (PDT) From: Vasily Khoruzhick To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] arm64: dts: allwinner: a64: add R_I2C controller Date: Tue, 5 Jun 2018 22:17:00 -0700 Message-Id: <20180606051702.6478-2-anarsoul@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180606051702.6478-1-anarsoul@gmail.com> References: <20180606051702.6478-1-anarsoul@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180605_221739_993199_0D314E65 X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vasily Khoruzhick , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Icenowy Zheng Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C. Add support for this I2C controller and the pinmux which doesn't conflict with RSB. Signed-off-by: Icenowy Zheng Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1b2ef28c42bd..dcf957b2e7c8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -46,6 +46,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -655,6 +656,18 @@ #reset-cells = <1>; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -666,6 +679,17 @@ interrupt-controller; #interrupt-cells = <3>; + + r_i2c_pins: i2c { + pins = "PL0", "PL1"; + function = "s_i2c"; + }; + + r_i2c_pins_a: i2c-a { + pins = "PL8", "PL9"; + function = "s_i2c"; + }; + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb";