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bh=v+KyweH6c0/5uR+9bkbPp68i2b0syMYrgorFm5gYS1E=; b=KlhqaAebEkJ10A9AnHR11g610LjgJ1RLh9SKv7rL0Kxb2nacq6InuUQKhDRY0RMPIZ tUVDi0R99gaXBPiGTCaG1/A4GygFxjiI+sFWWkxRTxTJS5LWM6Q4LtG2VFAa1GY9buj+ 97JJLHa+X7vHcejT1d5pF+l44cMYb9iMBB8RcT9oKwrupPJ17LVecxpLfIj9BZESwcRy B7SCMR9EJYiGpdBu/L6jtzlVFLaZynz1jMLJExpceg6V01pOgXHcYKYLe0pVSbmm0dmy 4UCN0okGintT0mrt43MuoXcRvUSs6zaHpzAdihpKCqsgSwr3KRO9Dl40Zu35w9QzQlW7 GE0A== X-Gm-Message-State: APt69E3jFrf+RPjQstZ0ls+OPo7JGVM7pRwPf3L3SfddV3LMUB2S3i4d xKxpOC3K7VAtuTAHb+Jwq8Szisl3 X-Google-Smtp-Source: ADUXVKJwohLx7IwSwx+PCKGRCzCU8fdTjJGb8AePoehAJ4X/Je1ykgfvvDEpFdOgFYr+Rjdj9fK7HQ== X-Received: by 2002:a50:a5ec:: with SMTP id b41-v6mr4314330edc.147.1528412329421; Thu, 07 Jun 2018 15:58:49 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.250]) by smtp.gmail.com with ESMTPSA id g30-v6sm4195716edb.5.2018.06.07.15.58.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jun 2018 15:58:48 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: spectre-v2: Try to set IBE bit for Cortex-A15 and Brahma-B15 Date: Thu, 7 Jun 2018 15:58:02 -0700 Message-Id: <20180607225804.28771-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.14.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180607_155902_497262_CE01CA53 X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Fainelli , Luca Scalabrino , marc.zyngier@arm.com, Russell King , open list , Tony Lindgren MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Per the ARM reference manual for the Cortex-A15, The ACTLR: Is a read/write register. Common to the Secure and Non-secure states. Is only accessible from PL1 or higher, with access rights that depend on the mode: * Read/write in Secure PL1 modes. * Read-only and write-ignored in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 0. * Read/write in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 1. In this case, all bits are write-ignored except for the SMP bit. We can attempt to set this bit from within the kernel, which helps avoiding firmware side modifications to set the IBE bit when that is impractical. We do this within __v7_ca15mp_setup and __v7_b15mp_setup because by then we already took those labels because the processors we run on do match. Signed-off-by: Florian Fainelli --- arch/arm/mm/proc-v7.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 6fe52819e014..a21cf3729efa 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -284,10 +284,16 @@ __v7_cr8mp_setup: b 1f __v7_ca7mp_setup: __v7_ca12mp_setup: + b 2f __v7_ca15mp_setup: __v7_b15mp_setup: +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 @ Enable IBE bit + mcr p15, 0, r0, c1, c0, 1 +#endif __v7_ca17mp_setup: - mov r10, #0 +2: mov r10, #0 1: adr r0, __v7_setup_stack_ptr ldr r12, [r0] add r12, r12, r0 @ the local stack