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Wed, 4 Jul 2018 09:04:57 +0000 Date: Wed, 4 Jul 2018 17:03:10 +0800 From: Jisheng Zhang To: Andy Shevchenko , Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH v2 3/3] serial: 8250_dw: add fractional divisor support Message-ID: <20180704170310.56772d77@xhacker.debian> In-Reply-To: <20180704165908.4bb8b090@xhacker.debian> References: <20180704165908.4bb8b090@xhacker.debian> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-Originating-IP: [124.74.246.114] X-ClientProxiedBy: KAWPR01CA0061.jpnprd01.prod.outlook.com (2603:1096:402:b::21) To DM5PR03MB2636.namprd03.prod.outlook.com (2603:10b6:3:43::10) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b3e79e8e-6ed4-463c-62af-08d5e18d37fd X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600053)(711020)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020); SRVR:DM5PR03MB2636; X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2636; 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The fractional divisor width is 4bits ~ 6bits. Now the preparation is done, it's easy to add the feature support. This patch firstly checks the component version during probe, if version >= 4.00a, then calculates the fractional divisor width, then setups dw specific get_divisor() and set_divisor() hook. Signed-off-by: Jisheng Zhang --- drivers/tty/serial/8250/8250_dw.c | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index aff04f1de3a5..b9630f633388 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -31,9 +31,12 @@ /* Offsets for the DesignWare specific registers */ #define DW_UART_USR 0x1f /* UART Status Register */ +#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ #define DW_UART_CPR 0xf4 /* Component Parameter Register */ #define DW_UART_UCV 0xf8 /* UART Component Version */ +#define DW_FRAC_MIN_VERS 0x3430302A + /* Component Parameter Register bits */ #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) #define DW_UART_CPR_AFCE_MODE (1 << 4) @@ -65,6 +68,7 @@ struct dw8250_data { unsigned int skip_autocfg:1; unsigned int uart_16550_compatible:1; + unsigned int dlf_size:3; }; static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) @@ -351,6 +355,33 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param) return param == chan->device->dev->parent; } +/* + * For version >= 4.00a, the dw uarts have a valid divisor latch fraction + * register. Calculate divisor with extra 4bits ~ 6bits fractional portion. + */ +static unsigned int dw8250_get_divisor(struct uart_port *p, + unsigned int baud, + unsigned int *frac) +{ + unsigned int quot; + struct dw8250_data *d = p->private_data; + + quot = DIV_ROUND_CLOSEST(p->uartclk << (d->dlf_size - 4), baud); + *frac = quot & (~0U >> (32 - d->dlf_size)); + + return quot >> d->dlf_size; +} + +static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, + unsigned int quot, unsigned int quot_frac) +{ + struct uart_8250_port *up = up_to_u8250p(p); + + serial_port_out(p, DW_UART_DLF >> p->regshift, quot_frac); + serial_port_out(p, UART_LCR, up->lcr | UART_LCR_DLAB); + serial_dl_write(up, quot); +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { if (p->dev->of_node) { @@ -414,6 +445,28 @@ static void dw8250_setup_port(struct uart_port *p) dev_dbg(p->dev, "Designware UART version %c.%c%c\n", (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); + /* + * For version >= 4.00a, the dw uarts have a valid divisor latch + * fraction register. Calculate the fractional divisor width. + */ + if (reg >= DW_FRAC_MIN_VERS) { + struct dw8250_data *d = p->private_data; + + if (p->iotype == UPIO_MEM32BE) { + iowrite32be(~0U, p->membase + DW_UART_DLF); + reg = ioread32be(p->membase + DW_UART_DLF); + } else { + writel(~0U, p->membase + DW_UART_DLF); + reg = readl(p->membase + DW_UART_DLF); + } + d->dlf_size = fls(reg); + + if (d->dlf_size) { + p->get_divisor = dw8250_get_divisor; + p->set_divisor = dw8250_set_divisor; + } + } + if (p->iotype == UPIO_MEM32BE) reg = ioread32be(p->membase + DW_UART_CPR); else