diff mbox

[v2,1/2] dt: bindings: Add bindings for SDHCI Synopsys DWC MSHC

Message ID 20180706152047.0b0a4944@xhacker.debian (mailing list archive)
State New, archived
Headers show

Commit Message

Jisheng Zhang July 6, 2018, 7:20 a.m. UTC
Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host
Controller can support eMMC/SD/SDIO. Add the bindings.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
 .../bindings/mmc/sdhci-of-dwcmshc.txt         | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt

Comments

Rob Herring (Arm) July 11, 2018, 4:12 p.m. UTC | #1
On Fri, Jul 06, 2018 at 03:20:47PM +0800, Jisheng Zhang wrote:
> Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host
> Controller can support eMMC/SD/SDIO. Add the bindings.
> 
> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> ---
>  .../bindings/mmc/sdhci-of-dwcmshc.txt         | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> new file mode 100644
> index 000000000000..ee4253b33be2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> @@ -0,0 +1,20 @@
> +* Synopsys DesignWare Cores Mobile Storage Host Controller
> +
> +Required properties:
> +- compatible: should be one of the following:
> +    "snps,dwcmshc-sdhci"

Needs to note that there must also be an SoC specific compatible.

> +- reg: offset and length of the register set for the device.
> +- interrupts: a single interrupt specifier.
> +- clocks: Array of clocks required for SDHCI; requires at least one for
> +    core clock.
> +- clock-names: Array of names corresponding to clocks property; shall be
> +    "core" for core clock and "bus" for optional bus clock.
> +
> +Example:
> +	sdhci2: sdhci@aa0000 {
> +		compatible = "snps,dwcmshc-sdhci";
> +		reg = <0xaa0000 0x1000>;
> +		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&emmcclk>;
> +		bus-width = <8>;
> +	}
> -- 
> 2.18.0
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Jisheng Zhang July 12, 2018, 2:06 a.m. UTC | #2
Hi Rob,

On Wed, 11 Jul 2018 10:12:06 -0600 Rob Herring wrote:

> On Fri, Jul 06, 2018 at 03:20:47PM +0800, Jisheng Zhang wrote:
> > Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host
> > Controller can support eMMC/SD/SDIO. Add the bindings.
> > 
> > Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> > ---
> >  .../bindings/mmc/sdhci-of-dwcmshc.txt         | 20 +++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > new file mode 100644
> > index 000000000000..ee4253b33be2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > @@ -0,0 +1,20 @@
> > +* Synopsys DesignWare Cores Mobile Storage Host Controller
> > +
> > +Required properties:
> > +- compatible: should be one of the following:
> > +    "snps,dwcmshc-sdhci"  
> 
> Needs to note that there must also be an SoC specific compatible.

Currently, there's no SoC specific code in this driver, so the binding could
be extended to SoC compatible if necessary. What do you think?

Thanks,
Jisheng
Rob Herring (Arm) July 16, 2018, 9:59 p.m. UTC | #3
On Thu, Jul 12, 2018 at 10:06:11AM +0800, Jisheng Zhang wrote:
> Hi Rob,
> 
> On Wed, 11 Jul 2018 10:12:06 -0600 Rob Herring wrote:
> 
> > On Fri, Jul 06, 2018 at 03:20:47PM +0800, Jisheng Zhang wrote:
> > > Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host
> > > Controller can support eMMC/SD/SDIO. Add the bindings.
> > > 
> > > Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> > > ---
> > >  .../bindings/mmc/sdhci-of-dwcmshc.txt         | 20 +++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > > new file mode 100644
> > > index 000000000000..ee4253b33be2
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> > > @@ -0,0 +1,20 @@
> > > +* Synopsys DesignWare Cores Mobile Storage Host Controller
> > > +
> > > +Required properties:
> > > +- compatible: should be one of the following:
> > > +    "snps,dwcmshc-sdhci"  
> > 
> > Needs to note that there must also be an SoC specific compatible.
> 
> Currently, there's no SoC specific code in this driver, so the binding could
> be extended to SoC compatible if necessary. What do you think?

Doesn't matter what's in the driver, it can use this compatible.

But experience has shown that a compatible for a licensed IP is never 
sufficient. There are versions of the blocks, configuration options, and 
integration differences.

I'm not asking you to add any SoC specific compatible now unless you 
are working on a particular SoC, but just state one is needed. 

Rob
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
new file mode 100644
index 000000000000..ee4253b33be2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
@@ -0,0 +1,20 @@ 
+* Synopsys DesignWare Cores Mobile Storage Host Controller
+
+Required properties:
+- compatible: should be one of the following:
+    "snps,dwcmshc-sdhci"
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: Array of clocks required for SDHCI; requires at least one for
+    core clock.
+- clock-names: Array of names corresponding to clocks property; shall be
+    "core" for core clock and "bus" for optional bus clock.
+
+Example:
+	sdhci2: sdhci@aa0000 {
+		compatible = "snps,dwcmshc-sdhci";
+		reg = <0xaa0000 0x1000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&emmcclk>;
+		bus-width = <8>;
+	}