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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id w16-v6sm57260335pfi.101.2018.07.11.19.33.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Jul 2018 19:33:53 -0700 (PDT) From: Andrey Smirnov To: Shawn Guo Subject: [PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config Date: Wed, 11 Jul 2018 19:33:36 -0700 Message-Id: <20180712023337.30112-2-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180712023337.30112-1-andrew.smirnov@gmail.com> References: <20180712023337.30112-1-andrew.smirnov@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180711_193405_026683_5C6F96FE X-CRM114-Status: GOOD ( 14.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nikita Yushchenko , Mark Rutland , devicetree@vger.kernel.org, Andrey Smirnov , linux-kernel@vger.kernel.org, Rob Herring , Andrew Lunn , linux-arm-kernel@lists.infradead.org, Fabio Estevam , cphealy@gmail.com, Lucas Stach MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT code to explicitly configure PAD_AUD3_BB_CK and avoid relying on defaults. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Shawn Guo Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov Reviewed-by: Andrew Lunn --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 2941a92d40f1..0bb42c00d72b 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5