From patchwork Tue Jul 24 11:45:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 10541925 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC67F1805 for ; Tue, 24 Jul 2018 11:48:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7E62260CD for ; Tue, 24 Jul 2018 11:48:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C62C42878F; Tue, 24 Jul 2018 11:48:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 60969260CD for ; Tue, 24 Jul 2018 11:48:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jNtXzIWtDFMhrgr7keUMIklAv0Yk1Gmvgaj7FHwO9f4=; b=A54CTF4XCwItWr LFXSuR6KwDO5ao8l3g9lFO/hLAlFV+IFhh4GofHLPyepcGQEpHGu31DcjiWDxU2CRYoZ0t61VgeF3 1HMXe1DWKRKMLZnSRPZEGjRSwzyGsS8rak5H6MsFLrnrIqwRYNlVj4rQDM7o/SlVEgD8uxLjjKhlj 9s5ej1WDPTTmEsuyZae97PdpHvulhHAaMbTxMNJKnJ2wZ27s3XkAJ/QARiAktqX6OE7FqH9XDJeXY V2iyGTYjI83y2+UzTUuhhDcrNG2FxKJr33ldzJsBJrixnPrEmdkU1KTCoSkL/3zHoA3sirRTUuI1j ONe7NyiCeTVUSp7L188Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhvnL-0008IU-0h; Tue, 24 Jul 2018 11:47:59 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fhvmC-00077t-9x for linux-arm-kernel@lists.infradead.org; Tue, 24 Jul 2018 11:47:01 +0000 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 04571103E3B15; Tue, 24 Jul 2018 19:46:35 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Tue, 24 Jul 2018 19:46:29 +0800 From: Shameer Kolothum To: , Subject: [PATCH v2 4/4] perf/smmuv3: Add MSI irq support Date: Tue, 24 Jul 2018 12:45:15 +0100 Message-ID: <20180724114515.21764-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> References: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180724_044648_973289_7E68BB12 X-CRM114-Status: GOOD ( 15.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, vkilari@codeaurora.org, neil.m.leeder@gmail.com, pabba@codeaurora.org, john.garry@huawei.com, will.deacon@arm.com, rruigrok@codeaurora.org, linuxarm@huawei.com, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds support for MSI based counter overflow interrupt. Signed-off-by: Shameer Kolothum --- drivers/perf/arm_smmuv3_pmu.c | 105 +++++++++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 21 deletions(-) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index b3dc394..ca69813 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -94,6 +94,10 @@ #define SMMU_PMCG_IRQ_CFG2 0xE64 #define SMMU_PMCG_IRQ_STATUS 0xE68 +/* MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 + #define SMMU_COUNTER_RELOAD BIT(31) #define SMMU_DEFAULT_FILTER_SEC 0 #define SMMU_DEFAULT_FILTER_SPAN 1 @@ -657,14 +661,89 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) return IRQ_HANDLED; } +static void smmu_pmu_free_msis(void *data) +{ + struct device *dev = data; + + platform_msi_domain_free_irqs(dev); +} + +static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + phys_addr_t doorbell; + struct device *dev = msi_desc_to_dev(desc); + struct smmu_pmu *pmu = dev_get_drvdata(dev); + + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + + writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); + writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, + pmu->reg_base + SMMU_PMCG_IRQ_CFG2); +} + +static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) +{ + struct msi_desc *desc; + struct device *dev = pmu->dev; + int ret; + + /* Clear MSI address reg */ + writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + + /* MSI supported or not */ + if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) + return; + + ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + if (ret) { + dev_warn(dev, "failed to allocate MSIs\n"); + return; + } + + desc = first_msi_entry(dev); + if (desc) + pmu->irq = desc->irq; + + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, smmu_pmu_free_msis, dev); +} + +static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) +{ + int irq, ret = -ENXIO; + + smmu_pmu_setup_msi(pmu); + + irq = pmu->irq; + if (irq) + ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq, + IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, + "smmu-v3-pmu", pmu); + return ret; +} + static int smmu_pmu_reset(struct smmu_pmu *smmu_pmu) { + int ret; + /* Disable counter and interrupt */ writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); + ret = smmu_pmu_setup_irq(smmu_pmu); + if (ret) { + dev_err(smmu_pmu->dev, "failed to setup irqs\n"); + return ret; + } + + /* Pick one CPU to be the preferred one to use */ + smmu_pmu->on_cpu = smp_processor_id(); + WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + smmu_pmu_disable(&smmu_pmu->pmu); return 0; } @@ -738,26 +817,8 @@ static int smmu_pmu_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "Failed to get valid irq for smmu @%pa\n", - &mem_resource_0->start); - return irq; - } - - err = devm_request_irq(dev, irq, smmu_pmu_handle_irq, - IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, - "smmu-pmu", smmu_pmu); - if (err) { - dev_err(dev, - "Unable to request IRQ%d for SMMU PMU counters\n", irq); - return err; - } - - smmu_pmu->irq = irq; - - /* Pick one CPU to be the preferred one to use */ - smmu_pmu->on_cpu = smp_processor_id(); - WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + if (irq > 0) + smmu_pmu->irq = irq; smmu_pmu->num_counters = get_num_counters(smmu_pmu); smmu_pmu->counter_present_mask = GENMASK(smmu_pmu->num_counters - 1, 0); @@ -765,7 +826,9 @@ static int smmu_pmu_probe(struct platform_device *pdev) SMMU_PMCG_CFGR_SIZE_MASK) >> SMMU_PMCG_CFGR_SIZE_SHIFT; smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0); - smmu_pmu_reset(smmu_pmu); + err = smmu_pmu_reset(smmu_pmu); + if (err) + return err; err = cpuhp_state_add_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);