| Message ID | 20180726003532.18751-11-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: allwinner: A64 boards DT updates | expand |
On Thu, Jul 26, 2018 at 01:35:24AM +0100, Andre Przywara wrote: > From: Samuel Holland <samuel@sholland.org> > > DCDC2 (polyphased with DCDC3) is supplying the power to the CPU. > Add a property to the CPU node to mark this connection. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts > index 6f85a05d2f4b..ec24b7379d6d 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts > @@ -101,6 +101,10 @@ > }; > }; > > +&cpu0 { > + cpu-supply = <®_dcdc2>; > +}; > + I'd rather not do that. As soon as we'll have OPPs in the DTSI, that means that cpufreq will be enabled on that board, while no one ever tested it. Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 6f85a05d2f4b..ec24b7379d6d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -101,6 +101,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci1 { status = "okay"; };