| Message ID | 20180822084110.14969-1-s.trumtrar@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges | expand |
Hi! Steffen Trumtrar <s.trumtrar@pengutronix.de> writes: > Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- > Changes in v2: > - set status to disabled, so there are no accidental users of > the bridges > > arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi > b/arch/arm/boot/dts/socfpga.dtsi > index b38f8c240558..11781f795de2 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -543,6 +543,20 @@ > clocks = <&l4_main_clk>; > }; > > + fpga_bridge2: fpga-bridge@ff600000 { > + compatible = > "altr,socfpga-fpga2hps-bridge"; > + reg = <0xff600000 0x100000>; > + resets = <&rst FPGA2HPS_RESET>; > + clocks = <&l4_main_clk>; > + status = "disabled"; > + }; > + > + fpga_bridge3: fpga-bridge@ffc25080 { > + compatible = > "altr,socfpga-fpga2sdram-bridge"; > + reg = <0xffc25080 0x4>; > + status = "disabled"; > + }; > + > fpgamgr0: fpgamgr@ff706000 { > compatible = "altr,socfpga-fpga-mgr"; > reg = <0xff706000 0x1000 Any opinion on this? There shouldn't be any accidental use of the bridges now with status=disabled. Best regards, Steffen
On Thu, Sep 13, 2018 at 2:27 AM Steffen Trumtrar <s.trumtrar@pengutronix.de> wrote: > > > Hi! > > Steffen Trumtrar <s.trumtrar@pengutronix.de> writes: > > > Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. > > > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > > --- > > Changes in v2: > > - set status to disabled, so there are no accidental users of > > the bridges > > > > arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/arch/arm/boot/dts/socfpga.dtsi > > b/arch/arm/boot/dts/socfpga.dtsi > > index b38f8c240558..11781f795de2 100644 > > --- a/arch/arm/boot/dts/socfpga.dtsi > > +++ b/arch/arm/boot/dts/socfpga.dtsi > > @@ -543,6 +543,20 @@ > > clocks = <&l4_main_clk>; > > }; > > > > + fpga_bridge2: fpga-bridge@ff600000 { > > + compatible = > > "altr,socfpga-fpga2hps-bridge"; > > + reg = <0xff600000 0x100000>; > > + resets = <&rst FPGA2HPS_RESET>; > > + clocks = <&l4_main_clk>; > > + status = "disabled"; > > + }; > > + > > + fpga_bridge3: fpga-bridge@ffc25080 { > > + compatible = > > "altr,socfpga-fpga2sdram-bridge"; > > + reg = <0xffc25080 0x4>; > > + status = "disabled"; > > + }; > > + > > fpgamgr0: fpgamgr@ff706000 { > > compatible = "altr,socfpga-fpga-mgr"; > > reg = <0xff706000 0x1000 > > Any opinion on this? There shouldn't be any accidental use of the > bridges now with status=disabled. Hi Steffen, Do you have a use case you need this for? I don't mind leaving it that way it is and letting people who are actually enabling the bridges in their designs add the whole node. Alan > > > Best regards, > Steffen > > -- > Pengutronix e.K. | Steffen Trumtrar > | > Industrial Linux Solutions | > http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany| Phone: > +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: > +49-5121-206917-5555|
Hi! Alan Tull <atull@kernel.org> writes: > On Thu, Sep 13, 2018 at 2:27 AM Steffen Trumtrar > <s.trumtrar@pengutronix.de> wrote: >> >> >> Hi! >> >> Steffen Trumtrar <s.trumtrar@pengutronix.de> writes: >> >> > Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. >> > >> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> >> > --- >> > Changes in v2: >> > - set status to disabled, so there are no accidental users >> > of >> > the bridges >> > >> > arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ >> > 1 file changed, 14 insertions(+) >> > >> > diff --git a/arch/arm/boot/dts/socfpga.dtsi >> > b/arch/arm/boot/dts/socfpga.dtsi >> > index b38f8c240558..11781f795de2 100644 >> > --- a/arch/arm/boot/dts/socfpga.dtsi >> > +++ b/arch/arm/boot/dts/socfpga.dtsi >> > @@ -543,6 +543,20 @@ >> > clocks = <&l4_main_clk>; >> > }; >> > >> > + fpga_bridge2: fpga-bridge@ff600000 { >> > + compatible = >> > "altr,socfpga-fpga2hps-bridge"; >> > + reg = <0xff600000 0x100000>; >> > + resets = <&rst FPGA2HPS_RESET>; >> > + clocks = <&l4_main_clk>; >> > + status = "disabled"; >> > + }; >> > + >> > + fpga_bridge3: fpga-bridge@ffc25080 { >> > + compatible = >> > "altr,socfpga-fpga2sdram-bridge"; >> > + reg = <0xffc25080 0x4>; >> > + status = "disabled"; >> > + }; >> > + >> > fpgamgr0: fpgamgr@ff706000 { >> > compatible = "altr,socfpga-fpga-mgr"; >> > reg = <0xff706000 0x1000 >> >> Any opinion on this? There shouldn't be any accidental use of >> the >> bridges now with status=disabled. > > Hi Steffen, > > Do you have a use case you need this for? > Yes, of course. I think all our SoCFPGA customers use these bridges. > I don't mind leaving it that way it is and letting people who > are > actually enabling the bridges in their designs add the whole > node. > Why do you think, that these bridges are different from the other ones? Or other IP blocks on the SoCFPGA even? This is the socfpga.dtsi file, it describes the hardware common to all Cyclone5 SoCs. All SoCs have these bridges, so why not add it? Best regards, Steffen
Hi! Steffen Trumtrar <s.trumtrar@pengutronix.de> writes: > Hi! > > Alan Tull <atull@kernel.org> writes: > >> On Thu, Sep 13, 2018 at 2:27 AM Steffen Trumtrar >> <s.trumtrar@pengutronix.de> wrote: >>> >>> >>> Hi! >>> >>> Steffen Trumtrar <s.trumtrar@pengutronix.de> writes: >>> >>> > Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. >>> > >>> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> >>> > --- >>> > Changes in v2: >>> > - set status to disabled, so there are no accidental users >>> > > of >>> > the bridges >>> > >>> > arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ >>> > 1 file changed, 14 insertions(+) >>> > >>> > diff --git a/arch/arm/boot/dts/socfpga.dtsi >>> > b/arch/arm/boot/dts/socfpga.dtsi >>> > index b38f8c240558..11781f795de2 100644 >>> > --- a/arch/arm/boot/dts/socfpga.dtsi >>> > +++ b/arch/arm/boot/dts/socfpga.dtsi >>> > @@ -543,6 +543,20 @@ >>> > clocks = <&l4_main_clk>; >>> > }; >>> > >>> > + fpga_bridge2: fpga-bridge@ff600000 { >>> > + compatible = >>> > "altr,socfpga-fpga2hps-bridge"; >>> > + reg = <0xff600000 0x100000>; >>> > + resets = <&rst FPGA2HPS_RESET>; >>> > + clocks = <&l4_main_clk>; >>> > + status = "disabled"; >>> > + }; >>> > + >>> > + fpga_bridge3: fpga-bridge@ffc25080 { >>> > + compatible = >>> > "altr,socfpga-fpga2sdram-bridge"; >>> > + reg = <0xffc25080 0x4>; >>> > + status = "disabled"; >>> > + }; >>> > + >>> > fpgamgr0: fpgamgr@ff706000 { >>> > compatible = "altr,socfpga-fpga-mgr"; >>> > reg = <0xff706000 0x1000 >>> >>> Any opinion on this? There shouldn't be any accidental use of >>> the >>> bridges now with status=disabled. >> >> Hi Steffen, >> >> Do you have a use case you need this for? >> > > Yes, of course. I think all our SoCFPGA customers use these > bridges. > >> I don't mind leaving it that way it is and letting people who >> are >> actually enabling the bridges in their designs add the whole >> node. >> > > Why do you think, that these bridges are different from the > other ones? > Or other IP blocks on the SoCFPGA even? > This is the socfpga.dtsi file, it describes the hardware common > to all > Cyclone5 SoCs. All SoCs have these bridges, so why not add it? > Any opinion on this? I still don't see why these bridges are different from the other IP cores. Best regards, Steffen
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b38f8c240558..11781f795de2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -543,6 +543,20 @@ clocks = <&l4_main_clk>; }; + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + status = "disabled"; + }; + fpgamgr0: fpgamgr@ff706000 { compatible = "altr,socfpga-fpga-mgr"; reg = <0xff706000 0x1000
Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- Changes in v2: - set status to disabled, so there are no accidental users of the bridges arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)