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Received: from inva021.nxp.com ([92.121.34.21]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g59nh-0008Qe-NV for linux-arm-kernel@lists.infradead.org; Wed, 26 Sep 2018 13:24:23 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 15BAA2002A2; Wed, 26 Sep 2018 15:23:02 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 132A72002D5; Wed, 26 Sep 2018 15:23:02 +0200 (CEST) Received: from fsr-ub1864-101.ea.freescale.net (fsr-ub1864-101.ea.freescale.net [10.171.82.97]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 6D3F0203C2; Wed, 26 Sep 2018 15:23:01 +0200 (CEST) From: laurentiu.tudor@nxp.com To: devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 18/22] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID Date: Wed, 26 Sep 2018 16:22:43 +0300 Message-Id: <20180926132247.10971-19-laurentiu.tudor@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180926132247.10971-1-laurentiu.tudor@nxp.com> References: <20180926132247.10971-1-laurentiu.tudor@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180926_142421_783639_AA250D5F X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharat.bhushan@nxp.com, madalin.bucur@nxp.com, shawnguo@kernel.org, roy.pledge@nxp.com, leoyang.li@nxp.com, robin.murphy@arm.com, davem@davemloft.net, Laurentiu Tudor MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Laurentiu Tudor The StreamID entering the SMMU is actually a concatenation of the SMMU TBU ID and the ICID configured in software. Since the TBU ID is internal to the SoC and since we want that the actual the ICID configured in software to enter the SMMU witout any additional set bits, mask out the TBU ID bits and leave only the relevant ICID bits to enter SMMU. Signed-off-by: Laurentiu Tudor --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 7eea2bace171..1f9b385007a8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -226,6 +226,7 @@ compatible = "arm,mmu-500"; reg = <0 0x9000000 0 0x400000>; dma-coherent; + stream-match-mask = <0x7f00>; #global-interrupts = <2>; #iommu-cells = <1>; interrupts = , diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 07a853a0aeaa..22bf3975492a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -232,6 +232,7 @@ compatible = "arm,mmu-500"; reg = <0 0x9000000 0 0x400000>; dma-coherent; + stream-match-mask = <0x7f00>; #global-interrupts = <2>; #iommu-cells = <1>; interrupts = ,