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bh=h7PHMbYpuEXpp+8XgIFSEXt+FJJ3QcGp+T82lkpHAH4=; b=pLG1crv6yzk3TL0kLLwPraJbDtCD+xb6FuahW9o3rtrDiOGIUyv2w9WwgcRrnf9B/N N4ILYnxyTVPIkGjAsvPi261A7xZm/l8JXjtxqTH2tKXCpBG8WlpW/0AZaaq5OnggFlfM ALrCW5XPsfeFOuIUaX5qQ5dcvAQLE4b9geMEECpTI7b9chQqLTXJvajtD4LnV06QnOvK fNE3oTvpH28JC8ognEk/aH063xZKqHW5g+5aRXxAOV4IoKDEFKjEY9vaEfyGmvb5Zlh6 OEfUaD2dBc+JQmGzMfFfUECYQjPQJmM50mvSTUAcwbR1eNjZdphIQjjF1PcZ3CGBHzzj oYOw== X-Gm-Message-State: ABuFfojkg2ml+cuJtYWLWG4eHf8x/Uctmn35rE5IX9ovzH3HSarJB4IK C8JMc/dTGIy9uoDwDDyasYXgRg== X-Google-Smtp-Source: ACcGV63oiscJEiP9nlZ/hvm2ilMa/7Ju7fl+feJ0Sd/gTtC1VKv0GWKXIM/Le/43UYW07D20gIaPcw== X-Received: by 2002:a63:7107:: with SMTP id m7-v6mr9830760pgc.73.1538049004209; Thu, 27 Sep 2018 04:50:04 -0700 (PDT) Received: from localhost.localdomain ([183.82.230.83]) by smtp.gmail.com with ESMTPSA id v36-v6sm3744872pgn.85.2018.09.27.04.49.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 04:50:03 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Vasily Khoruzhick , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 07/12] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits Date: Thu, 27 Sep 2018 17:18:45 +0530 Message-Id: <20180927114850.24565-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180927114850.24565-1-jagan@amarulasolutions.com> References: <20180927114850.24565-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180927_045035_864894_54CF0345 X-CRM114-Status: GOOD ( 15.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jagan Teki Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP TCON DRQ set bits for non-burst DSI mode can computed via horizontal front porch instead of front porch + sync timings. Since there no documentation for TCON_DRQ_REG(0x7c) register this change is taken as reference from BPI-M64-bsp. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 599284971ab6..9918fdb990ff 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, struct mipi_dsi_device *device = dsi->device; u32 val = 0; - if ((mode->hsync_end - mode->hdisplay) > 20) { + if ((mode->hsync_start - mode->hdisplay) > 20) { /* Maaaaaagic */ - u16 drq = (mode->hsync_end - mode->hdisplay) - 20; + u16 drq = (mode->hsync_start - mode->hdisplay) - 20; drq *= mipi_dsi_pixel_format_to_bpp(device->format); drq /= 32;