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Wed, 3 Oct 2018 11:56:48 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 3 Oct 2018 11:56:48 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w93GuZMK030968; Wed, 3 Oct 2018 11:56:45 -0500 From: Vignesh R To: Boris Brezillon , Marek Vasut , Rob Herring Subject: [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller Date: Wed, 3 Oct 2018 22:26:03 +0530 Message-ID: <20181003165603.2579-4-vigneshr@ti.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181003165603.2579-1-vigneshr@ti.com> References: <20181003165603.2579-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181003_125713_985617_CF0FCE61 X-CRM114-Status: GOOD ( 13.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yogesh Gaur , Vignesh R , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Brian Norris , Linux ARM Mailing List Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Signed-off-by: Vignesh R --- drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index e24db817154e..48b00e75a879 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -101,6 +101,7 @@ struct cqspi_st { #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 #define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -898,6 +899,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) case SNOR_PROTO_1_1_4: f_pdata->data_width = CQSPI_INST_TYPE_QUAD; break; + case SNOR_PROTO_1_1_8: + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; + break; default: return -EINVAL; } @@ -1205,6 +1209,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) SNOR_HWCAPS_READ_FAST | SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | + SNOR_HWCAPS_READ_1_1_8 | SNOR_HWCAPS_PP, }; struct platform_device *pdev = cqspi->pdev; @@ -1456,6 +1461,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,k2g-qspi", .data = (void *)CQSPI_NEEDS_WR_DELAY, }, + { + .compatible = "ti,am654-ospi", + .data = (void *)CQSPI_NEEDS_WR_DELAY, + }, { /* end of table */ } };