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Fri, 5 Oct 2018 03:23:23 +0000 From: Pankaj Bansal To: Leo Li Subject: [PATCH 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage Date: Fri, 5 Oct 2018 14:25:04 +0530 Message-Id: <20181005085505.29024-2-pankaj.bansal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005085505.29024-1-pankaj.bansal@nxp.com> References: <20181005085505.29024-1-pankaj.bansal@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.143.30.134] X-ClientProxiedBy: BM1PR01CA0081.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::21) To HE1PR0402MB3324.eurprd04.prod.outlook.com (2603:10a6:7:81::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: db0e8539-533c-4fa0-6b24-08d62a71e937 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:HE1PR0402MB3324; X-Microsoft-Exchange-Diagnostics: 1; HE1PR0402MB3324; 3:e7jGirJcRPM9taGGwDBblixFbqvBl0M/MMI1XTuGwFMRctyJKI/D4RpWiikaRFVeL0pr6uuLkd/qxW0T/hl8NOUBe6X0BCaAjvOxz9+LowJA/sRKhbNv4MGl4UxyI4KWgrif/6kG3+sdGCbKhE6Q24BaNLqYIw/TQziD6szOomNnLZqlLfuOwyk38D5XmNEx4d0Xk+/t7Dy8sR9fSJ//wgpgwo1vfTMPSvxhPPyV+bFyzVks05BxxXhgGhHEJZ4L; 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Signed-off-by: Pankaj Bansal --- .../bindings/soc/fsl/qixis_ctrl.txt | 33 ++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt new file mode 100644 index 000000000000..bc2950cab71d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt @@ -0,0 +1,33 @@ +* QIXIS FPGA block + +an FPGA-based system controller, called “Qixis”, which +manages several critical system features, including: +• Configuration switch monitoring +• Power on/off sequencing +• Reset sequencing +• Power supply configuration +• Board configuration +• hardware configuration +• Background power data collection (DCM) +• Fault monitoring +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only) +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on) +• I2C master for remote board control even with no DUT available + +The qixis registers are accessible over one or more system-specific interfaces, +typically I2C, JTAG or an embedded processor. + +Required properties: + + - compatible : string, must contain "fsl,fpga-qixis-i2c" + - reg : i2c address of the qixis device. + +Examples: + /* The FPGA node */ + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + } +