@@ -52,4 +52,7 @@ extern unsigned long socfpga_cpu1start_addr;
#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
+/* Clock manager defines */
+#define SOCFPGA_ENABLE_PLL_REG 0xA0
+
#endif
@@ -31,6 +31,7 @@ void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
+void __iomem *clkmgr_base_addr;
static void __init socfpga_sysmgr_init(void)
{
@@ -51,6 +52,10 @@ static void __init socfpga_sysmgr_init(void)
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
rst_manager_base_addr = of_iomap(np, 0);
+ np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
+ clkmgr_base_addr = of_iomap(np, 0);
+ WARN_ON(!clkmgr_base_addr);
+
np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
sdr_ctl_base_addr = of_iomap(np, 0);
}
@@ -80,6 +85,9 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
{
u32 temp;
+ /* Turn on all periph PLL clocks */
+ writel(0xffff, clkmgr_base_addr + SOCFPGA_ENABLE_PLL_REG);
+
temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
if (mode == REBOOT_HARD)