[13/26] kvm: arm64: Switch to per VM IPA limit

Message ID	20181019125901.185478-14-marc.zyngier@arm.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Marc Zyngier <marc.zyngier@arm.com> To: Paolo Bonzini <pbonzini@redhat.com>, =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com> Subject: [PATCH 13/26] kvm: arm64: Switch to per VM IPA limit Date: Fri, 19 Oct 2018 13:58:48 +0100 Message-Id: <20181019125901.185478-14-marc.zyngier@arm.com> In-Reply-To: <20181019125901.185478-1-marc.zyngier@arm.com> References: <20181019125901.185478-1-marc.zyngier@arm.com> MIME-Version: 1.0 Precedence: list Cc: Mark Rutland <mark.rutland@arm.com>, zhong jiang <zhongjiang@huawei.com>, kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Punit Agrawal <punit.agrawal@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Kristina Martsenko <kristina.martsenko@arm.com>, Dongjiu Geng <gengdongjiu@huawei.com>, Eric Auger <eric.auger@redhat.com>, James Morse <james.morse@arm.com>, Robin Murphy <robin.murphy@arm.com>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
Series	[01/26] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table \| expand [01/26] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table [02/26] kvm: arm/arm64: Remove spurious WARN_ON [03/26] kvm: arm64: Add helper for loading the stage2 setting for a VM [04/26] arm64: Add a helper for PARange to physical shift conversion [05/26] kvm: arm64: Clean up VTCR_EL2 initialisation [06/26] kvm: arm/arm64: Allow arch specific configurations for VM [07/26] kvm: arm64: Configure VTCR_EL2 per VM [08/26] kvm: arm/arm64: Prepare for VM specific stage2 translations [09/26] kvm: arm64: Prepare for dynamic stage2 page table layout [10/26] kvm: arm64: Make stage2 page table layout dynamic [11/26] kvm: arm64: Dynamic configuration of VTTBR mask [12/26] kvm: arm64: Configure VTCR_EL2.SL0 per VM [13/26] kvm: arm64: Switch to per VM IPA limit [14/26] vgic: Add support for 52bit guest physical address [15/26] kvm: arm64: Add 52bit support for PAR to HPFAR conversoin [16/26] kvm: arm64: Set a limit on the IPA size [17/26] kvm: arm64: Limit the minimum number of page table levels [18/26] kvm: arm64: Allow tuning the physical address size for VM [19/26] KVM: arm/arm64: Rename kvm_arm_config_vm to kvm_arm_setup_stage2 [20/26] KVM: arm64: Drop __cpu_init_stage2 on the VHE path [21/26] arm64: KVM: Remove some extra semicolon in kvm_target_cpu [22/26] KVM: arm/arm64: Ensure only THP is candidate for adjustment [23/26] KVM: arm64: Fix caching of host MDCR_EL2 value [24/26] arm/arm64: KVM: Rename function kvm_arch_dev_ioctl_check_extension() [25/26] arm/arm64: KVM: Enable 32 bits kvm vcpu events support [26/26] KVM: arm64: Safety check PSTATE when entering guest and handle IL

Message ID

20181019125901.185478-14-marc.zyngier@arm.com (mailing list archive)

State

New, archived

Headers

From: Marc Zyngier <marc.zyngier@arm.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
 =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>
Subject: [PATCH 13/26] kvm: arm64: Switch to per VM IPA limit
Date: Fri, 19 Oct 2018 13:58:48 +0100
Message-Id: <20181019125901.185478-14-marc.zyngier@arm.com>
In-Reply-To: <20181019125901.185478-1-marc.zyngier@arm.com>
References: <20181019125901.185478-1-marc.zyngier@arm.com>
MIME-Version: 1.0
Precedence: list
Cc: Mark Rutland <mark.rutland@arm.com>, zhong jiang <zhongjiang@huawei.com>,
 kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
 Catalin Marinas <catalin.marinas@arm.com>,
 Punit Agrawal <punit.agrawal@arm.com>,
 Christoffer Dall <christoffer.dall@arm.com>,
 Kristina Martsenko <kristina.martsenko@arm.com>,
 Dongjiu Geng <gengdongjiu@huawei.com>, Eric Auger <eric.auger@redhat.com>,
 James Morse <james.morse@arm.com>, Robin Murphy <robin.murphy@arm.com>,
 kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
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 linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org

Series

[01/26] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table | expand

Commit Message

Marc Zyngier Oct. 19, 2018, 12:58 p.m. UTC

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Now that we can manage the stage2 page table per VM, switch the
configuration details to per VM instance. The VTCR is updated
with the values specific to the VM based on the configuration.
We store the IPA size and the number of stage2 page table levels
for the guest already in VTCR. Decode it back from the vtcr
field wherever we need it.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/include/asm/kvm_arm.h        | 2 ++
 arch/arm64/include/asm/kvm_mmu.h        | 2 +-
 arch/arm64/include/asm/stage2_pgtable.h | 2 +-
 arch/arm64/kvm/reset.c                  | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index f913adb44f93..e4240568cc18 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -197,6 +197,8 @@ 
 	VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
 
 #define VTCR_EL2_FLAGS			(VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
+#define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
+
 /*
  * ARM VMSAv8-64 defines an algorithm for finding the translation table
  * descriptors in section D4.2.8 in ARM DDI 0487C.a.
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index ac3ca9690bad..77b1af9e64db 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -142,7 +142,7 @@  static inline unsigned long __kern_hyp_va(unsigned long v)
  */
 #define KVM_PHYS_SHIFT	(40)
 
-#define kvm_phys_shift(kvm)		KVM_PHYS_SHIFT
+#define kvm_phys_shift(kvm)		VTCR_EL2_IPA(kvm->arch.vtcr)
 #define kvm_phys_size(kvm)		(_AC(1, ULL) << kvm_phys_shift(kvm))
 #define kvm_phys_mask(kvm)		(kvm_phys_size(kvm) - _AC(1, ULL))
 
diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h
index 36a0a1165003..c62fe118a898 100644
--- a/arch/arm64/include/asm/stage2_pgtable.h
+++ b/arch/arm64/include/asm/stage2_pgtable.h
@@ -43,7 +43,7 @@ 
  */
 #define stage2_pgtable_levels(ipa)	ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
 #define STAGE2_PGTABLE_LEVELS		stage2_pgtable_levels(KVM_PHYS_SHIFT)
-#define kvm_stage2_levels(kvm)		stage2_pgtable_levels(kvm_phys_shift(kvm))
+#define kvm_stage2_levels(kvm)		VTCR_EL2_LVLS(kvm->arch.vtcr)
 
 /*
  * With all the supported VA_BITs and 40bit guest IPA, the following condition
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 1ced1e37374e..2bf41e007390 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -160,7 +160,7 @@  int kvm_arm_config_vm(struct kvm *kvm, unsigned long type)
 	if (phys_shift > KVM_PHYS_SHIFT)
 		phys_shift = KVM_PHYS_SHIFT;
 	vtcr |= VTCR_EL2_T0SZ(phys_shift);
-	vtcr |= VTCR_EL2_LVLS_TO_SL0(kvm_stage2_levels(kvm));
+	vtcr |= VTCR_EL2_LVLS_TO_SL0(stage2_pgtable_levels(phys_shift));
 
 	/*
 	 * Enable the Hardware Access Flag management, unconditionally

[13/26] kvm: arm64: Switch to per VM IPA limit

Commit Message

Patch