[01/26] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table

Commit Message

Marc Zyngier Oct. 19, 2018, 12:58 p.m. UTC

From: Suzuki K Poulose <[e-mail]>

So far we have only supported 3 level page table with fixed IPA of
40bits, where PUD is folded. With 4 level page tables, we need
to check if the PUD entry is valid or not. Fix stage2_flush_memslot()
to do this check, before walking down the table.

Acked-by: Christoffer Dall <[e-mail]>
Acked-by: Marc Zyngier <[e-mail]>
Reviewed-by: Eric Auger <[e-mail]>
Signed-off-by: Suzuki K Poulose <[e-mail]>
Signed-off-by: Marc Zyngier <[e-mail]>
---
 virt/kvm/arm/mmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Patch

diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index ed162a6c57c5..ee7ce8fa4a12 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -412,7 +412,8 @@  static void stage2_flush_memslot(struct kvm *kvm,
 	pgd = kvm->arch.pgd + stage2_pgd_index(addr);
 	do {
 		next = stage2_pgd_addr_end(addr, end);
-		stage2_flush_puds(kvm, pgd, addr, next);
+		if (!stage2_pgd_none(*pgd))
+			stage2_flush_puds(kvm, pgd, addr, next);
 	} while (pgd++, addr = next, addr != end);
 }