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Thu, 25 Oct 2018 05:59:20 +0000 From: "Kulkarni, Ganapatrao" To: "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v7 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver Thread-Topic: [PATCH v7 1/2] perf, uncore: Adding documentation for ThunderX2 pmu uncore driver Thread-Index: AQHUbCffy5t4TQ8Iz0uSu+j9ZDwgxQ== Date: Thu, 25 Oct 2018 05:59:20 +0000 Message-ID: <20181025055833.28471-2-ganapatrao.kulkarni@cavium.com> References: <20181025055833.28471-1-ganapatrao.kulkarni@cavium.com> In-Reply-To: <20181025055833.28471-1-ganapatrao.kulkarni@cavium.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BM1PR0101CA0040.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1a::26) To BN7PR07MB5298.namprd07.prod.outlook.com (2603:10b6:408:2d::28) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Ganapatrao.Kulkarni@cavium.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [111.93.218.67] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:BN7PR07MB4626; H:BN7PR07MB5298.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 4IrmrK8gnO1WQnVG276AlfTh4T63hj/pF/42lyj2gApdUbg66HOFtTeMVW9mwIHw+L1d7mheHQOncHos/D/4D8KXZrxMp3+X5lyMf6+++nFSKP7P3y5RDwgnsJdNgurNFyuGpp4Ickuor3K6u3MfQfvaZwcQ5I6w9Ihkp46cfx/zr+Sy8y2sqeaqm/FKHoUu/DOIP7lL9NFdJxaX8CBw5boe6G0C5MzEvkkIL4oTqp2QMaHc/IABmgI2PKxzYLj9tHR9VkqUoYtexSJi82JHEbFEX4PHIK9myqzd9wDfI1HeUs+JF8/yhWvRYDFjGCT18th0w+JuxJH8zFu7idHR9W9wxB4lWmVcRyLzfzW3tEo= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9ead966c-d779-4931-e9b4-08d63a3f00f3 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2018 05:59:20.5989 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR07MB4626 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181024_225931_400678_71802D1C X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "Nair, Jayachandran" , "suzuki.poulose@arm.com" , "gklkml16@gmail.com" , Jan Glauber , "Will.Deacon@arm.com" , "Lomovtsev, Vadim" , "Richter, Robert" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 106 +++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.txt diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt new file mode 100644 index 000000000000..9f5dd7459e68 --- /dev/null +++ b/Documentation/perf/thunderx2-pmu.txt @@ -0,0 +1,106 @@ + +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) +========================================================================== + +ThunderX2 SoC PMU consists of independent system wide per Socket PMUs such +as Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). + +DMC has 8 interleave channels and L3C has 16 interleave tiles. Events are +sampled for default channel(i.e channel 0) and prorated to total number of +channels/tiles. + +DMC and L3C, Each PMU supports up to 4 counters. Counters are independently +programmable and can be started and stopped individually. Each counter can +be set to sample specific perf events. Counters are 32 bit and do not support +overflow interrupt; they are sampled at every 2 seconds. + +PMU UNCORE (perf) driver: + +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. +Each of the PMUs provides description of its available events +and configuration options in sysfs. + see /sys/devices/uncore_ + +S is socket id. +Each PMU can be used to sample up to 4 events simultaneously. + +The "format" directory describes format of the config (event ID). +The "events" directory provides configuration templates for all +supported event types that can be used with perf tool. + +For example, "uncore_dmc_0/cnt_cycles/" is an +equivalent of "uncore_dmc_0/config=0x1/". + +Each perf driver also provides a "cpumask" sysfs attribute, which contains a +single CPU ID of the processor which is likely to be used to handle all the +PMU events. It will be the first online CPU from the NUMA node of the PMU device. + +Example for perf tool use: + +perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1 + +perf stat -a -e \ +uncore_dmc_0/cnt_cycles/,\ +uncore_dmc_0/data_transfers/,\ +uncore_dmc_0/read_txns/,\ +uncore_dmc_0/write_txns/ sleep 1 + +perf stat -a -e \ +uncore_l3c_0/read_request/,\ +uncore_l3c_0/read_hit/,\ +uncore_l3c_0/inv_request/,\ +uncore_l3c_0/inv_hit/ sleep 1 + +The driver does not support sampling, therefore "perf record" will +not work. Per-task (without "-a") perf sessions are not supported. + +L3C events: +============ + +read_request: + Number of Read requests received by the L3 Cache. + This include Read as well as Read Exclusives. + +read_hit: + Number of Read requests received by the L3 cache that were hit + in the L3 (Data provided form the L3) + +writeback_request: + Number of Write Backs received by the L3 Cache. These are basically + the L2 Evicts and writes from the PCIe Write Cache. + +inv_nwrite_request: + This is the Number of Invalidate and Write received by the L3 Cache. + Also Writes from IO that did not go through the PCIe Write Cache. + +inv_nwrite_hit + This is the Number of Invalidate and Write received by the L3 Cache + That were a hit in the L3 Cache. + +inv_request: + Number of Invalidate request received by the L3 Cache. + +inv_hit: + Number of Invalidate request received by the L3 Cache that were a + hit in L3. + +evict_request: + Number of Evicts that the L3 generated. + +NOTE: +1. Granularity of all these events counter value is cache line length(64 Bytes). +2. L3C cache Hit Ratio = (read_hit + inv_nwrite_hit + inv_hit) / (read_request + inv_nwrite_request + inv_request) + +DMC events: +============ +cnt_cycles: + Count cycles (Clocks at the DMC clock rate) + +write_txns: + Number of 64 Bytes write transactions received by the DMC(s) + +read_txns: + Number of 64 Bytes Read transactions received by the DMC(s) + +data_transfers: + Number of 64 Bytes data transferred to or from DRAM.