| Message ID | 20181105074842.21988-1-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/3] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width | expand |
On Mon, Nov 5, 2018 at 3:49 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > MUX bits for MMC clock register range are 25:24 where 24 is shift > and 2 is width So fix the width number from 3 to 2. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> However, given that most of the other module clocks have bits 26:24 as their mux bits, and the mmc clocks use 3 bits to denote the values and corresponding clock parents, I would have appreciated you actually doing tests to confirm which of these errors is the actual error, and not just say "the user manual says so", because it is not always completely correct.
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2193e1495086..e2bc612f1d3e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -411,7 +411,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -419,7 +419,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); @@ -427,7 +427,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 0, 4, /* M */ 8, 2, /* N */ - 24, 3, /* mux */ + 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0);
MUX bits for MMC clock register range are 25:24 where 24 is shift and 2 is width So fix the width number from 3 to 2. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v2: - none drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)