From patchwork Mon Nov 5 12:06:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 10668081 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 186F91751 for ; Mon, 5 Nov 2018 12:11:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01C2429617 for ; Mon, 5 Nov 2018 12:11:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E5680296D1; Mon, 5 Nov 2018 12:11:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 560E129617 for ; Mon, 5 Nov 2018 12:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:Message-Id: In-Reply-To:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: References:List-Owner; bh=C7iD9lXScADZvWR1ulXhyf3qriGEwOM6+rR5Vh1m0ew=; b=PjD Bqg3upcqXJ0TjRXr4OGIfvYWMyxJq2z8OmM9K/AG25wISfhPrgYfvJyqDGP4NyS4Lexd7nMsvUr1i 3JyxibzoKwJe5LWIgQg7QPj74x1acD+4a/LbYGFVqp4vzw5yW6UjXR/gdsUkPshkeE2uluHFVZcMF MRalKptyxu8KisY8m4W6aZ2Rl08B7FGAkt6Y1WBmZHNFaZdlp7yIxx6fimiUpWmCnLW3/KkUMcsUc fK9dq8C8UYm/S2oB96qS9IJ7fSyr20bHvQPU47bN5Q7svQgQnjjwDZvSxhSykfkVLPGTmHkcfBaLr 0WUvkSPtxeThR2Ru2pJo4ciWfNxzOOQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gJdj8-0000tp-E4; Mon, 05 Nov 2018 12:11:30 +0000 Received: from heliosphere.sirena.org.uk ([2a01:7e01::f03c:91ff:fed4:a3b6]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gJdeL-0005yb-Qh; Mon, 05 Nov 2018 12:07:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=3T14e23X9qeNGqUae23BIOBMT5yjuVjTEjhQKi2p73E=; b=KTxSL8j5SJau XWLVyFPNywKnxCa5QIYyuF63KcI0QO+PDyljBewPVmv/Di6+9oApwrP64Ws0o1V4b9FcRcAXn6Vvm 7FHELD4o0J8y6k8iPpL2I+XIk2Ir/qk5YTpZiI4/u1UfCDaFCvZHOsQtEifWZJgaWMseu2urMXQxu 4OW7o=; Received: from cpc102320-sgyl38-2-0-cust46.18-2.cable.virginm.net ([82.37.168.47] helo=debutante.sirena.org.uk) by heliosphere.sirena.org.uk with esmtpa (Exim 4.89) (envelope-from ) id 1gJde9-0008NG-OX; Mon, 05 Nov 2018 12:06:21 +0000 Received: by debutante.sirena.org.uk (Postfix, from userid 1000) id 755631124D98; Mon, 5 Nov 2018 12:06:21 +0000 (GMT) From: Mark Brown To: Emil Renner Berthing Subject: Applied "spi: rockchip: set min/max speed" to the spi tree In-Reply-To: <20181031105711.19575-11-esmil@mailme.dk> Message-Id: <20181105120621.755631124D98@debutante.sirena.org.uk> Date: Mon, 5 Nov 2018 12:06:21 +0000 (GMT) X-Bad-Reply: In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181105_040634_257597_BB920492 X-CRM114-Status: GOOD ( 19.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Addy Ke , Heiko Stuebner , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-rockchip@lists.infradead.org, Mark Brown , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: rockchip: set min/max speed has been applied to the spi tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From 420b82f842941a32adf309ca1b193adfc77616b0 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 31 Oct 2018 11:57:07 +0100 Subject: [PATCH] spi: rockchip: set min/max speed The driver previously checked each transfer if the requested speed was higher than possible with the current spi clock rate and raised the clock rate accordingly. However, there is no check to see if the spi clock was actually set that high and no way to dynamically lower the spi clock rate again. So it seems any potiential users of this functionality are better off just setting the spi clock rate at init using the assigned-clock-rates devicetree property. Removing this dynamic spi clock rate raising allows us let the spi framework handle min/max speeds for us. Signed-off-by: Emil Renner Berthing Tested-by: Heiko Stuebner Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 52 +++++++++++++++----------------------- 1 file changed, 20 insertions(+), 32 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index ba60cbcd45c2..d1b3ba2b1532 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -115,6 +115,10 @@ /* Bit fields in SER, 2bit */ #define SER_MASK 0x3 +/* Bit fields in BAUDR */ +#define BAUDR_SCKDV_MIN 2 +#define BAUDR_SCKDV_MAX 65534 + /* Bit fields in SR, 5bit */ #define SR_MASK 0x1f #define SR_BUSY (1 << 0) @@ -147,7 +151,7 @@ #define TXDMA (1 << 1) /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ -#define MAX_SCLK_OUT 50000000 +#define MAX_SCLK_OUT 50000000U /* * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, @@ -171,12 +175,11 @@ struct rockchip_spi { /*depth of the FIFO buffer */ u32 fifo_len; - /* max bus freq supported */ - u32 max_freq; + /* frequency of spiclk */ + u32 freq; u8 n_bytes; u32 rsd_nsecs; - u32 speed; const void *tx; const void *tx_end; @@ -191,11 +194,6 @@ static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); } -static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) -{ - writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); -} - static inline void wait_for_idle(struct rockchip_spi *rs) { unsigned long timeout = jiffies + msecs_to_jiffies(5); @@ -451,7 +449,6 @@ static void rockchip_spi_config(struct rockchip_spi *rs, struct spi_device *spi, struct spi_transfer *xfer, bool use_dma) { - u32 div = 0; u32 dmacr = 0; int rsd = 0; @@ -477,30 +474,17 @@ static void rockchip_spi_config(struct rockchip_spi *rs, dmacr |= RF_DMA_EN; } - if (WARN_ON(rs->speed > MAX_SCLK_OUT)) - rs->speed = MAX_SCLK_OUT; - - /* the minimum divisor is 2 */ - if (rs->max_freq < 2 * rs->speed) { - clk_set_rate(rs->spiclk, 2 * rs->speed); - rs->max_freq = clk_get_rate(rs->spiclk); - } - - /* div doesn't support odd number */ - div = DIV_ROUND_UP(rs->max_freq, rs->speed); - div = (div + 1) & 0xfffe; - /* Rx sample delay is expressed in parent clock cycles (max 3) */ - rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), + rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->freq >> 8), 1000000000 >> 8); if (!rsd && rs->rsd_nsecs) { pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", - rs->max_freq, rs->rsd_nsecs); + rs->freq, rs->rsd_nsecs); } else if (rsd > 3) { rsd = 3; pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", - rs->max_freq, rs->rsd_nsecs, - rsd * 1000000000U / rs->max_freq); + rs->freq, rs->rsd_nsecs, + rsd * 1000000000U / rs->freq); } cr0 |= rsd << CR0_RSD_OFFSET; @@ -520,9 +504,12 @@ static void rockchip_spi_config(struct rockchip_spi *rs, writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); - spi_set_clk(rs, div); - - dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); + /* the hardware only supports an even clock divisor, so + * round divisor = spiclk / speed up to nearest even number + * so that the resulting speed is <= the requested speed + */ + writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), + rs->regs + ROCKCHIP_SPI_BAUDR); } static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) @@ -551,7 +538,6 @@ static int rockchip_spi_transfer_one( return -EINVAL; } - rs->speed = xfer->speed_hz; rs->n_bytes = xfer->bits_per_word >> 3; rs->tx = xfer->tx_buf; @@ -631,7 +617,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) spi_enable_chip(rs, false); rs->dev = &pdev->dev; - rs->max_freq = clk_get_rate(rs->spiclk); + rs->freq = clk_get_rate(rs->spiclk); if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", &rsd_nsecs)) @@ -653,6 +639,8 @@ static int rockchip_spi_probe(struct platform_device *pdev) master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; + master->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); master->set_cs = rockchip_spi_set_cs; master->transfer_one = rockchip_spi_transfer_one;