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b=NF+fLJ6DkEP/ErtOgd+gTIOOvd/90BCScUtAjFMU0IX3reCG2/HfKmVR92gM6CyG37 uLbwAHt31ih/6+kG5ehEbjModwQYfqEjFk51WSAOn3jOpY7clXjUGLN9PGXqz541ZISA 5B/iGhp0QqO9TqHY0H301K6a5OESjwcNJnhNuJAshQ2U0zO1VN2mH0r+OSz7GF72pqZW GHGjoJy3blvy5LnujZxnaIoU9HYpLM+TvqO0VOx/TdRDqpvJXbrxfIPhlQllCgc8VDfQ S9dw4uJN2sOLpCZYuZccheIbClLj7QNRXaNEetrYUqOdvpXlUT5LLkxkidQNlyGfOAAH r+kw== X-Gm-Message-State: AGRZ1gKbCO5UpEufS/qIpqk7C3lRuGzRgiLHFiIyoADWJPZi32AmmrYJ JYED8+jKWm4gr9KO2Wxr8CiDnj0dTNI= X-Google-Smtp-Source: AJdET5eLsaxyn/ylvkDR0xUuGgvx+oVEtqJ+PIAu1u/7oExF+zLbdi59VliolV5O+zHLKuJre7cntA== X-Received: by 2002:a5d:5544:: with SMTP id g4-v6mr19994048wrw.222.1541443497679; Mon, 05 Nov 2018 10:44:57 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:3117:2b29:5ef7:a9e5]) by smtp.gmail.com with ESMTPSA id y21-v6sm19329761wma.36.2018.11.05.10.44.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 10:44:56 -0800 (PST) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: compressed: move BE32 handling into head.S Date: Mon, 5 Nov 2018 19:44:36 +0100 Message-Id: <20181105184438.19494-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181105184438.19494-1-ard.biesheuvel@linaro.org> References: <20181105184438.19494-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181105_104508_697438_BB8CD6FB X-CRM114-Status: GOOD ( 13.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nicolas.pitre@linaro.org, linux@armlinux.org.uk, Ard Biesheuvel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The BE switch only takes 3 instructions, and is currently pulled into the main startup code by the linker, which is not the nicest way to do this. Let's just pull the code into head.S and enable it using preprocessor conditionals. Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/Makefile | 8 -------- arch/arm/boot/compressed/big-endian.S | 14 -------------- arch/arm/boot/compressed/head.S | 5 +++++ 3 files changed, 5 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 01bf2585a0fa..d1862621556f 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -47,14 +47,6 @@ ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y) OBJS += head-sharpsl.o endif -ifeq ($(CONFIG_CPU_ENDIAN_BE32),y) -ifeq ($(CONFIG_CPU_CP15),y) -OBJS += big-endian.o -else -# The endian should be set by h/w design. -endif -endif - # # We now have a PIC decompressor implementation. Decompressors running # from RAM should not define ZTEXTADDR. Decompressors running directly diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S deleted file mode 100644 index 88e2a88d324b..000000000000 --- a/arch/arm/boot/compressed/big-endian.S +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/arm/boot/compressed/big-endian.S - * - * Switch CPU into big endian mode. - * Author: Nicolas Pitre - */ - - .section ".start", #alloc, #execinstr - - mrc p15, 0, r0, c1, c0, 0 @ read control reg - orr r0, r0, #(1 << 7) @ enable big endian mode - mcr p15, 0, r0, c1, c0, 0 @ write control reg - diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index da93f419d1f4..55c227077207 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -222,6 +222,11 @@ not_angel: #ifdef CONFIG_CPU_XSCALE bl __XScale_start #endif +#if defined(CONFIG_CPU_ENDIAN_BE32) && defined(CONFIG_CPU_CP15) + mrc p15, 0, r0, c1, c0, 0 @ read control reg + orr r0, r0, #(1 << 7) @ enable big endian mode + mcr p15, 0, r0, c1, c0, 0 @ write control reg +#endif #ifdef CONFIG_AUTO_ZRELADDR /*