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Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gJv4g-0003kN-98 for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2018 06:42:56 +0000 X-UUID: fc6f19e270dc40a194f4aabcabbca711-20181106 X-UUID: fc6f19e270dc40a194f4aabcabbca711-20181106 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 151291692; Tue, 06 Nov 2018 14:42:23 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 6 Nov 2018 14:42:22 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 6 Nov 2018 14:42:22 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring Subject: [PATCH v1 03/11] clk: mediatek: Disable tuner_en before change PLL rate Date: Tue, 6 Nov 2018 14:41:58 +0800 Message-ID: <20181106064206.17535-5-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181106064206.17535-1-weiyi.lu@mediatek.com> References: <20181106064206.17535-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181106_064254_595704_40CA6BD0 X-CRM114-Status: GOOD ( 15.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Owen Chen PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Signed-off-by: Owen Chen --- drivers/clk/mediatek/clk-pll.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 0ec2c62d9383..cca9002de91b 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -27,7 +27,7 @@ #define CON0_BASE_EN BIT(0) #define CON0_PWR_ON BIT(0) #define CON0_ISO_EN BIT(1) -#define CON0_PCW_CHG BIT(31) +#define CON1_PCW_CHG BIT(31) #define AUDPLL_TUNER_EN BIT(31) @@ -95,9 +95,31 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, { u32 con1, val; int pll_en; + u32 tuner_en = 0; + u32 tuner_en_mask; + void __iomem *tuner_en_addr = NULL; pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; + /* disable tuner */ + if (pll->tuner_en_addr) { + tuner_en_addr = pll->tuner_en_addr; + tuner_en_mask = BIT(pll->data->tuner_en_bit); + } else if (pll->tuner_addr) { + tuner_en_addr = pll->tuner_addr; + tuner_en_mask = AUDPLL_TUNER_EN; + } + + if (tuner_en_addr) { + val = readl(tuner_en_addr); + tuner_en = val & tuner_en_mask; + + if (tuner_en) { + val &= ~tuner_en_mask; + writel(val, tuner_en_addr); + } + } + /* set postdiv */ val = readl(pll->pd_addr); val &= ~(POSTDIV_MASK << pll->data->pd_shift); @@ -118,12 +140,19 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, con1 = readl(pll->base_addr + REG_CON1); if (pll_en) - con1 |= CON0_PCW_CHG; + con1 |= CON1_PCW_CHG; writel(con1, pll->base_addr + REG_CON1); if (pll->tuner_addr) writel(con1 + 1, pll->tuner_addr); + /* restore tuner_en */ + if (tuner_en_addr && tuner_en) { + val = readl(tuner_en_addr); + val |= tuner_en_mask; + writel(val, tuner_en_addr); + } + if (pll_en) udelay(20); }