| Message ID | 20181115145013.3378-4-paul.kocialkowski@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Cedrus support for the Allwinner H5 and A64 platforms | expand |
On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski <paul.kocialkowski@bootlin.com> wrote: > > Unlike in previous generations, the system-control register range is not > limited to a size of 0x30 on the H3. In particular, the EMAC clock > configuration register (accessed through syscon) is at offset 0x30 in > that range. > > Extend the register size to its full range (0x1000) as a result. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Other than the subject format, Acked-by: Chen-Yu Tsai <wens@csie.org>
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 35d025af7deb..7157d954fb8c 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -136,7 +136,7 @@ soc { system-control@1c00000 { compatible = "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x30>; + reg = <0x01c00000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges;
Unlike in previous generations, the system-control register range is not limited to a size of 0x30 on the H3. In particular, the EMAC clock configuration register (accessed through syscon) is at offset 0x30 in that range. Extend the register size to its full range (0x1000) as a result. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)