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[2003:dc:d717:a100:b85a:ce58:5a88:5c51]) by smtp.googlemail.com with ESMTPSA id x142-v6sm50950160wmd.20.2018.11.15.14.47.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Nov 2018 14:47:09 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org Subject: [PATCH v2 2/2] clocksource: meson6_timer: implement ARM delay timer Date: Thu, 15 Nov 2018 23:46:57 +0100 Message-Id: <20181115224657.14736-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181115224657.14736-1-martin.blumenstingl@googlemail.com> References: <20181115224657.14736-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181115_144722_204480_AB998587 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl --- drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 23c7638e2bb3..84bd9479c3f8 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_ARM +#include +#endif + #define MESON_ISA_TIMER_MUX 0x00 #define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) #define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) @@ -54,6 +58,18 @@ static void __iomem *timer_base; +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + static u64 notrace meson6_timer_sched_read(void) { return (u64)readl(timer_base + MESON_ISA_TIMERE); @@ -192,6 +208,12 @@ static int __init meson6_timer_init(struct device_node *node) clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + return 0; } TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",