From patchwork Wed Nov 28 09:30:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 10702145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 269C013AD for ; Wed, 28 Nov 2018 09:33:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13C3F2CEF2 for ; Wed, 28 Nov 2018 09:33:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 111B82CEC6; Wed, 28 Nov 2018 09:33:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 851DF2CEF3 for ; Wed, 28 Nov 2018 09:33:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q/PRJQ4qkxUA7Xpe8RjhYKGV8jilcLPpIdYsaAOx3/8=; b=PHZERilp2DhF2y UfzUGlYp6L8elzWj+Rr/zzOI5NbwORTaNYE11ANeLk0K2mUg4fHAWP7BLPp7W9oiF6yrC9ZYJMUz2 rabIIZvz6XzV2YFj1Ru5W7Xbly/oqPAND7s0oH6wJTKAU4x/zbAzonpM/JyDVnnJXq8dpdiXPbqz+ Sa6JKbRCGIIHnM6WzxtW2UIE/mRBWwrs5CrHq9GRwZlGmGPq+aeg2tUY0FSmOWCMGRDg12UWJ3S4K vD99eVO4UovkU6n4pRIpdOM1Z1TN6cET05o6FVqq5x/OQQh7L3skkkS2DM/sNRSH9KJ5eu8mTENLx nrsLaQTITy/LtmBOga6Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRwDX-0002IX-4m; Wed, 28 Nov 2018 09:33:11 +0000 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76] helo=wens.csie.org) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRwBL-0008Np-OY for linux-arm-kernel@lists.infradead.org; Wed, 28 Nov 2018 09:31:04 +0000 Received: by wens.csie.org (Postfix, from userid 1000) id 600EF600DC; Wed, 28 Nov 2018 17:30:28 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Alexandre Belloni , Alessandro Zummo , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Subject: [PATCH 06/15] rtc: sun6i: Add support for different variants Date: Wed, 28 Nov 2018 17:30:03 +0800 Message-Id: <20181128093013.24442-7-wens@csie.org> X-Mailer: git-send-email 2.20.0.rc1 In-Reply-To: <20181128093013.24442-1-wens@csie.org> References: <20181128093013.24442-1-wens@csie.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_013056_549869_FD6F8579 X-CRM114-Status: GOOD ( 19.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Amongst the Allwinner SoCs that have seen some kind of coverage by the linux-sunxi community, whether it be mainline Linux or U-boot support, or just available datasheets, most newer chips use the RTC design first seen in the A31 (sun6i). Overall there have been some minor differences. This patch covers the following: - average clock rate of the internal RC oscillator + presence of fixed and adjustable prescaler for this clock - availability of an external (to the SoC) clock output One major difference regarding the H6 is the 24 MHz crystal is now routed through the RTC, as a digitally compensated oscillator (DCXO). This is not covered in this patch and will be supported later. Other differences are either unrelated to RTC or clock functionality, such as boot or crypto related registers, or the driver simply doesn't use the feature in question. One example of the latter is the calibration function for the RC oscillator. We consider this clock to be very bad and avoid using it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- drivers/rtc/rtc-sun6i.c | 58 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 8edd9e1ec007..d1866d90b9ef 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -118,9 +118,30 @@ #define SUN6I_YEAR_MAX 2033 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) +/* + * There are other differences between models, including: + * + * - number of GPIO pins that can be configured to hold a certain level + * - crypto-key related registers (H5, H6) + * - boot process related (super standby, secondary processor entry address) + * registers (R40, H6) + * - SYS power domain controls (R40) + * - DCXO controls (H6) + * - RC oscillator calibration (H6) + * + * These functions are not covered by this driver. + */ +struct sun6i_rtc_clk_data { + unsigned long rc_osc_rate; + unsigned int fixed_prescaler : 16; + unsigned int has_prescaler : 1; + unsigned int has_out_clk : 1; +}; + struct sun6i_rtc_dev { struct rtc_device *rtc; struct device *dev; + const struct sun6i_rtc_clk_data *data; void __iomem *base; int irq; unsigned long alarm; @@ -139,14 +160,19 @@ static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); - u32 val; + u32 val = 0; val = readl(rtc->base + SUN6I_LOSC_CTRL); if (val & SUN6I_LOSC_CTRL_EXT_OSC) return parent_rate; - val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); - val &= GENMASK(4, 0); + if (rtc->data->fixed_prescaler) + parent_rate /= rtc->data->fixed_prescaler; + + if (rtc->data->has_prescaler) { + val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); + val &= GENMASK(4, 0); + } return parent_rate / (val + 1); } @@ -185,7 +211,8 @@ static const struct clk_ops sun6i_rtc_osc_ops = { .set_parent = sun6i_rtc_osc_set_parent, }; -static void __init sun6i_rtc_clk_init(struct device_node *node) +static void __init sun6i_rtc_clk_init(struct device_node *node, + const struct sun6i_rtc_clk_data *data) { struct clk_hw_onecell_data *clk_data; struct sun6i_rtc_dev *rtc; @@ -200,6 +227,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node) if (!rtc) return; + rtc->data = data; clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL); if (!clk_data) { kfree(rtc); @@ -228,7 +256,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node) rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, "rtc-int-osc", NULL, 0, - 667000, + rtc->data->rc_osc_rate, 300000000); if (IS_ERR(rtc->int_osc)) { pr_crit("Couldn't register the internal oscillator\n"); @@ -271,8 +299,18 @@ static void __init sun6i_rtc_clk_init(struct device_node *node) err: kfree(clk_data); } -CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc", - sun6i_rtc_clk_init); + +static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { + .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ + .has_prescaler = 1, +}; + +static void __init sun6i_a31_rtc_clk_init(struct device_node *node) +{ + sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); +} +CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", + sun6i_a31_rtc_clk_init); static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) { @@ -579,6 +617,12 @@ static int sun6i_rtc_probe(struct platform_device *pdev) return 0; } +/* + * As far as RTC functionality goes, all models are the same. The + * datasheets claim that different models have different number of + * registers available for non-volatile storage, but experiments show + * that all SoCs have 16 registers available for this purpose. + */ static const struct of_device_id sun6i_rtc_dt_ids[] = { { .compatible = "allwinner,sun6i-a31-rtc" }, { /* sentinel */ },