Message ID | 20181204092548.3038-15-josephl@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Tegra210 DFLL support | expand |
On 04/12/2018 09:25, Joseph Lo wrote: > Add CPU clocks for Tegra210. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > index a6db62157442..e2baf52fe1af 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > @@ -1304,6 +1304,12 @@ > device_type = "cpu"; > compatible = "arm,cortex-a57"; > reg = <0>; > + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, > + <&tegra_car TEGRA210_CLK_PLL_X>, > + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, > + <&dfll>; > + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; > + clock-latency = <300000>; > }; > > cpu@1 { > Acked-by: Jon Hunter <jonathanh@nvidia.com> Cheers Jon
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a6db62157442..e2baf52fe1af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 {
Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)